Non-Volatile Memory Array With Resistive Sense Element Block Erase and Uni-Directional Write
First Claim
1. A non-volatile memory cell, comprising:
- a transistor comprising source and drain regions spanned by a gate region; and
a resistive sense element (RSE) connected to the drain region of the transistor, the RSE programmed to a first resistance by flowing a first write current through the RSE and then through the drain and source regions of the transistor, the RSE programmed to a second resistance by flowing a second write current through the drain region and then through the RSE, the second write current bypassing the source region.
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Abstract
A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device.
30 Citations
20 Claims
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1. A non-volatile memory cell, comprising:
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a transistor comprising source and drain regions spanned by a gate region; and a resistive sense element (RSE) connected to the drain region of the transistor, the RSE programmed to a first resistance by flowing a first write current through the RSE and then through the drain and source regions of the transistor, the RSE programmed to a second resistance by flowing a second write current through the drain region and then through the RSE, the second write current bypassing the source region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor stack, comprising:
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a p doped substrate in which spaced-apart first and second n+ doped regions and a p+ doped contact area are formed, the first n+ doped region and the p+ doped contact area respectively maintained at a fixed reference voltage; a gate structure which spans a channel between the first and second n+ doped regions to form a transistor; and a resistive sense element (RSE) connected to the second n+ doped region, the RSE programmed to a first resistance by flowing a transistor body-drain current from the p+ doped contact area to the second n+ doped region and then to the RSE, the RSE programmed to a different second resistance by flowing a transistor source-drain current through the RSE to the second n+ doped region, and across the transistor channel to the first n+ doped region. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method comprising:
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providing a memory cell comprising a transistor connected in series with a resistive sense element (RSE), the transistor comprising source and drain regions spanned by a gate region, the RSE connected to the drain region, and the source region maintained at a fixed reference voltage; programming the RSE to a first electrical resistance by flowing a first write current through the memory cell that sequentially passes through the RSE and then through the drain and source regions of the transistor; and programming the RSE to a different, second resistance by flowing a second write current through the memory cell that sequentially passes through the drain region and then through the RSE, the second write current bypassing the source region of the transistor. - View Dependent Claims (18, 19, 20)
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Specification