Variable short interframe space

• US 20110026446A1
• Filed: 08/03/2009
• Published: 02/03/2011
• Est. Priority Date: 08/03/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Stacey, Robert
• Granted Patent: US 8,335,198 B2
• Time in Patent Office: Days
• US Class Current: 370/310
• CPC Class Codes: H04L 1/1614 using bitmaps
• CPC Class Codes: H04L 1/1854 Scheduling and prioritising arrangements
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365

Abstract

Apparatuses, systems, and methods for transmitting data frames over data networks with varying Interframe Space (IFS) times are disclosed. A system embodiment may comprise a mobile computing device with an integrated wireless networking card. The card may receive a transmission of several data frames. While receiving the several data frames, the networking card may determine that a response will need to be transmitted back to the sending station after the sending station sends the last frame of data. After a short period of delay following the end of the last transmitted frame the card may immediately begin transmitting a preamble of the response, while still demodulating and processing data of the transmitted frames. Upon finishing data processing of the remaining frames, the card may generate the content for the rest of the response, such as a block acknowledgment.

Claims

1. A method, comprising:

receiving, by a first station, data of an aggregate of multiple data frames, wherein transmission of the aggregate comprises one of a 2.4 gigahertz (GHz), 5 GHz, and 60 GHz wireless transmission from a second station;

determining, by the first station, to transmit a response related to reception of the data; and

beginning transmission of the response upon completion of the transmission of the aggregate, wherein the beginning of the transmission occurs before the first station completes the media access control (MAC) processing of demodulated data of the aggregate.

2. The method of claim 1, wherein the beginning transmission of the response comprises initiating transmission of a preamble of the response.

3. The method of claim 2, further comprising:

completing the MAC processing of a last frame of the multiple data frames.

4. The method of claim 3, further comprising:

determining, by the first station, at least some of the content of the response upon the completing the MAC processing of the last frame.

5. The method of claim 4, further comprising:

transmitting the at least some of the content upon completion of the transmission of the preamble, wherein the response comprises a block acknowledge (BA).

6. The method of claim 1, wherein the determining to transmit the response occurs before completion of the transmission of the aggregate by the second station.

7. An apparatus, comprising:

a receiver to receive a transmission of an aggregate of multiple data frames, wherein the receiver comprises a demodulator to demodulate data of the aggregate;

a media access control (MAC) module to process demodulated data of the receiver; and

a response module to generate a response to the transmission of the aggregate, wherein the response comprises a preamble and response content, wherein further the response module is configured to generate the preamble as the MAC module processes demodulated data of the aggregate.

8. The apparatus of claim 7, further comprising a transmitter to transmit the response.

9. The apparatus of claim 8, wherein the response module is configured to generate the response content after the MAC module processes a final frame of the multiple data frames.

10. The apparatus of claim 9, wherein the MAC module is configured to process demodulated data while the demodulator demodulates data, wherein further the response module is configured to generate the preamble while the demodulator demodulates data of the aggregate.

11. The apparatus of claim 10, wherein the response module comprises a processor coupled to the MAC module to enable the MAC module to process the demodulated data.

12. The apparatus of claim 11, wherein the processor is coupled to the modulator, and dynamic random access memory (DRAM), wherein further the response content comprises a portion of a block acknowledge (BA).

13. The apparatus of claim 8, wherein transmitter and the receiver comprise a transceiver coupled to a single antenna, wherein further the response module is configured to switch the apparatus from a receive mode to a transmit mode upon completion of the transmission of the aggregate.

14. The apparatus of claim 8, wherein transmitter is coupled to a transmission antenna and the receiver is coupled to a reception antenna.

15. The apparatus of claim 8, wherein the response module is configured to begin transmitting the preamble between fixed values of SIFSmin and SIFSmax.

16. The apparatus of claim 15, wherein SIFS min equals 0.3 μ

s and SIFSmax equals 2 μ

s.

17. A system, comprising:

a receiver coupled to an antenna, the receiver to receive data of a plurality of data frames, wherein the plurality is transmitted via one of a 2.4 gigahertz (GHz), 5 GHz, and 60 GHz wireless network;

a processing module coupled to the receiver to process the plurality of data frames and decide to transmit a response for the plurality of data frames, wherein the processing module is configured to make the decision to transmit the response while the receiver receives data of the plurality; and

a transmitter to transmit the response, wherein the processing module is configured to generate a second portion of the response while the transmitter transmits a first portion.

18. The system of claim 17, wherein the processing module comprises a media access control (MAC) module and a physical (PHY) module, wherein the MAC module is configured to process data of the plurality while the PHY module demodulates and decodes data of the plurality.

19. The system of claim 18, wherein the processing module comprises a processor coupled the MAC module and coupled to memory, wherein further the memory comprises dynamic random access memory (DRAM).

20. The system of claim 19, wherein the PHY module is configured to decode data of a final frame of the plurality while preparing the transmitter to transmit the response, wherein further the MAC module is configured to process data of the final frame while the transmitter transmits the first portion.