CLOCK SWITCHING CIRCUITS AND METHODS

• US 20110026656A1
• Filed: 02/28/2009
• Published: 02/03/2011
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: NPX B.V.
• Original Assignee: NPX B.V.
• Inventors: Vos, Antonius Maria Hubertus, Gregie, Neil
• Granted Patent: US 8,533,517 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

For use in systems having multiple potential clock sources, circuitry and methods are used for selecting from among multiple clock sources and for preventing switching to an inactive clock source. Such clock switching circuitry and methods are used to detect an activity-status indication of the clock sources, generate a selection based update-enable signal responsive to the detected activity-status indication of the selected clock source, update a clock select input signal in response to a clock switch request for switching to the selected clock source and based on the generated selection based update-enable signal, and control switching to the selected clock source based on the updated clock select input signal.

Claims

1. For use in a system having multiple clock sources, a method for switching to a selected one of the multiple clock sources comprising:

detecting an activity-status indication of the selected clock source;

generating a selection based update-enable signal responsive to the detected activity-status indication of the selected clock source;

in response to a clock switch request for switching to the selected clock source and based on the generated selection based update-enable signal, updating a clock select input signal; and

controlling switching to the selected clock source based on the updated clock select input signal.

2. The method of claim 1, further comprising detecting activity-status indication for each of the multiple clock sources.

3. The method of claim 1, wherein generating the selection based update-enable signal includes producing a selection-enable signal when the selected clock source is indicated as active, and producing a selection-disable signal when the selected clock source is indicated as inactive.

4. The method of claim 3, wherein a select register stores a clock value representative of the clock select input signal, and wherein updating the clock select input signal comprises overwriting the clock value in the select register to identify the selected clock source in response to production of the update-enable signal.

5. The method of claim 3, wherein a select register stores a clock value representative of the clock select input signal, and wherein updating the clock select input signal comprises preventing overwriting of the clock value in the select register in response to production of the selection-disable signal.

6. The method of claim 1, wherein controlling switching includes using the clock select input signal as the control input of a multiplexer that selects from among the clock sources.

7. The method of claim 1, wherein the multiple clock sources include at least one internal clock source and at least one external clock source.

8. The method of claim 1, wherein the multiple clock sources include clock sources having different phases or different frequencies.

9. The method of claim 1, further comprising providing a switching-status signal back to the system indicating whether the clock switch request was allowed or prevented by the step of controlling switching to the selected clock source.

10. For use in a system having multiple clock sources, a circuit for switching to a selected one of the multiple clock sources comprising:

detection circuitry to detect an activity-status indication of each of the clock sources;

update-enable circuitry to generate a selection based update-enable signal responsive to the activity-status indication of the selected clock source;

control circuitry to update a clock select input signal responsive to a clock switch request for switching to the selected clock source and based on the generated selection based update-enable signal; and

switching circuitry to switch to the selected clock source based on the updated clock select input signal.

11. The circuit of claim 10, wherein the detection circuitry includes a plurality of detectors, each detector associated with one of the multiple clock sources and adapted to produce a logical 1 if the associated clock source is active and a logical 0 if the associated clock source is inactive.

12. The circuit of claim 10, wherein the update-enable circuitry includes a block of comparators that compares the clock select input signal with static values associated with each clock input source.

13. The circuit of claim 10, wherein the control circuitry includes a multiplexer that selects between overwriting a value in a select register to reflect the selected clock source and maintaining the value in the select register to reflect a current clock source, the value in the select register being used as the updated clock select input signal.

14. The circuit of claim 10, wherein the switching circuitry includes a multiplexer that selects an output clock source from among the multiple clock sources based on the updated clock select input signal.

15. The circuit of claim 10, wherein the multiple clock sources include at least one internal clock source and at least one external clock source.

16. The circuit of claim 10, wherein the multiple clock sources include clock sources having different phases.

17. The circuit of claim 10, wherein the multiple clock sources include clock sources having different frequencies.