Detecting Chip Alterations with Light Emission

• US 20110026806A1
• Filed: 07/30/2009
• Published: 02/03/2011
• Est. Priority Date: 07/30/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Stellari, Franco, Pfeiffer, Dirk, Heidel, David F., Wisnieff, Robert L., Culp, James, Song, Peilin, Polson, Anthony D., Bernstein, Kerry
• Granted Patent: US 9,075,106 B2
• Time in Patent Office: Days
• US Class Current: 382/145
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.

Claims

1. A method comprising:

obtaining an emission map of a circuit to be tested for alterations;

obtaining an emission map of a reference circuit; and

comparing said emission map of said circuit to be tested with said emission map of said reference circuit, to determine presence of said alterations.

2. The method of claim 1, further comprising normalizing at least one of said emission map of said circuit to be tested and said emission map of said reference circuit, prior to said comparing step.

3. The method of claim 2, wherein said comparing step comprises subtraction.

4. The method of claim 2, wherein said comparing step comprises differentiation.

5. The method of claim 2, wherein said comparing step comprises applying a two-dimensional correlation function.

6. The method of claim 2, wherein said emission map of said circuit to be tested is obtained by an emission tool.

7. The method of claim 6, further comprising applying liquid cooling to said circuit to be tested while obtaining said emission map.

8. The method of claim 6, further comprising initializing said circuit to be tested prior to said obtaining of said emission map of said circuit to be tested.

9. The method of claim 2, wherein said reference circuit is physically available and wherein said emission map of said reference circuit is obtained by an emission tool.

10. The method of claim 9, further comprising initializing said reference circuit prior to said obtaining of said emission map of said reference circuit.

11. The method of claim 2, wherein said emission map of said reference circuit is obtained by simulation.

12. The method of claim 11, wherein said simulation comprises:

calculating a leakage current for each of a plurality of devices of said reference circuit, based on a layout database and a state vector;

dividing said reference circuit into a plurality of sub-Nyquist tiles;

summing said leakage current for each of said devices in each given one of said sub-Nyquist tiles to obtain a resultant grid;

oversampling said resultant grid; and

applying a functional form to obtain said emission map from said leakage currents in said resultant grid.

13. The method of claim 12, wherein said functional form is based on data gathered using a calibration circuit.

14. The method of claim 2, wherein said emission map of said circuit to be tested is obtained using a microscope with an objective lens.

15. The method of claim 14, further comprising introducing a solid immersion lens between said objective lens of said microscope and said circuit to be tested.

16. The method of claim 2, wherein said alterations comprise tampering with unused logic.

17. The method of claim 16, wherein said unused logic comprises unused gate arrays.

18. An apparatus comprising:

means for obtaining an emission map of a circuit to be tested for alterations;

means for obtaining an emission map of a reference circuit; and

means for comparing said emission map of said circuit to be tested with said emission map of said reference circuit, to determine presence of said alterations.

19. The apparatus of claim 18, further comprising means for normalizing at least one of said emission map of said circuit to be tested and said emission map of said reference circuit, prior to said comparing step.

20. An apparatus comprising:

a memory; and

at least one processor, coupled to said memory, said processor being operative to;

obtain an emission map of a circuit to be tested for alterations;

obtain an emission map of a reference circuit; and

compare said emission map of said circuit to be tested with said emission map of said reference circuit, to determine presence of said alterations.

21. The apparatus of claim 20, wherein said at least one processor is further operative to normalize at least one of said emission map of said circuit to be tested and said emission map of said reference circuit, prior to said comparing step.

22. The apparatus of claim 21, further comprising an emission prediction module embodied in a computer readable storage medium, said at least one processor being operative to execute said emission prediction module to obtain said emission map of said reference circuit.

23. The apparatus of claim 21, wherein said processor is operative to execute said emission prediction module by:

calculating a leakage current for each of a plurality of devices of said reference circuit, based on a layout database and a state vector;

dividing said reference circuit into a plurality of sub-Nyquist tiles;

summing said leakage current for each of said devices in each given one of said sub-Nyquist tiles to obtain a resultant grid;

oversampling said resultant grid; and

applying a functional form to obtain said emission map from said leakage currents in said resultant grid.

24. A computer program product comprising a computer readable storage medium including computer usable program code, the computer program product including:

computer usable program code for calculating a leakage current for each of a plurality of devices of a reference circuit, based on a layout database and a state vector;

computer usable program code for dividing said reference circuit into a plurality of sub-Nyquist tiles;

computer usable program code for summing said leakage current for each of said devices in each given one of said sub-Nyquist tiles to obtain a resultant grid;

computer usable program code for oversampling said resultant grid; and

computer usable program code for applying a functional form to obtain an emission map from said leakage currents in said resultant grid.

25. The computer program product of claim 24, wherein said functional form is based on data gathered using a calibration circuit.