Low Temperature Wafer Level Processing for MEMS Devices

• US 20110027930A1
• Filed: 03/11/2009
• Published: 02/03/2011
• Est. Priority Date: 03/11/2008
• Status: Active Grant

• Current Assignee: McGill University
• Original Assignee: McGill University
• Inventors: Lemoine, Dominique, Nabki, Frederic, Cicek, Paul-Vahe, El-Gamal, Mourad
• Granted Patent: US 8,409,901 B2
• Time in Patent Office: Days
• US Class Current: 438/51
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H03H 3/007 for the manufacture of electromechanical resonators or networks
• CPC Class Codes: H03H 9/10 Mounting in enclosures constructional combinations of enclosure with electromechanical and other electronic elements H03H9/0538

Abstract

Microelectromechanical systems (MEMS) are small integrated devices or systems that combine electrical and mechanical components. It would be beneficial for such MEMS devices to be integrated with silicon CMOS electronics and packaged in controlled environments and support industry standard mounting interconnections such as solder bump through the provisioning of through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and stresses placed on metallization membranes are not present in packaging conventional CMOS electronics. Accordingly there is provided a means of reinforcing the through-wafer vias for such integrated MEMS-CMOS circuits by in filling a predetermined portion of the through-wafer electrical vias with low temperature deposited ceramic materials which are deposited at temperatures below 350° C., and potentially to below 250° C., thereby allowing the re-inforcing ceramic to be deposited after fabrication of the CMOS electronics.

Claims

1. A method comprising:

providing a first substrate, the first substrate comprising at least one feed-through through a thickness of the first substrate from a first surface to a second surface;

providing electrical interconnection by way of the at least one feed-through from the first surface to the second surface;

fabricating at least one microelectromechanical systems (MEMS) device directly onto the second surface of the first substrate;

providing a second substrate, the second substrate comprising at least one recess dimensioned so as to accept the at least one MEMS device fabricated on the first substrate;

positioning the second substrate with respect to the first substrate such that the at least one MEMS device is thereby contained within a cavity formed by the first substrate and the at least one recess; and

bonding the second substrate and first substrate together.

2. A method according to claim 1 wherein,

fabricating the at least one MEMS device comprises fabricating the at least one MEMS with a low temperature MEMS process incorporating at least one structural layer and having a maximum temperature exposure to the substrate of at least one of 250°

C. and 350°

C.

3. A method according to claim 2 wherein,

the at least one structural layer is selected from the group comprising silicon, silicon dioxide, silicon nitride, silicon germanium, silicon oxynitride, carbon, aluminum oxide, and silicon carbide.

4. A method according to claim 2 wherein,

the at least one structural layer is at least one of a polymer, a material exhibiting piezoelectric properties, and a material exhibiting piezoresistive properties.

5. A method according to claim 1 wherein,

the at least one feed-through is a via through the substrate from the first surface to the second surface, and at least a first predetermined portion of the via filled with a first material and a second predetermined portion of the via filled with a second material.

6. A method according to claim 5 wherein,

the at least one of the first material and the second material is selected from the group comprising silicon, silicon dioxide, silicon nitride, silicon oxynitride, carbon, aluminum oxide, and silicon carbide.

7. A method according to claim 5 wherein,

the at least one of the first material and the second material is at least one of a polymer, a metal, a material exhibiting piezoelectric properties, and a material exhibiting piezoresistive properties.

8. A method according to claim 5 wherein,

the at least one of the first material and the second material is a filler material, the filler material filling the cavity formed by the first substrate and the at least one recess.

9. A method according to claim 1 wherein,

the first substrate is a silicon substrate, a predetermined portion of the silicon substrate having fabricated therein at least one integrated circuit, wherein the predetermined region of the silicon substrate with the at least one integrated circuit fabricated therein is the second surface of the first substrate.

10. A method according to claim 1 wherein,

forming the cavity between the first and second substrates and bonding the second substrate and first substrate together results in at least one of a seal, an hermetic seal, a cavity containing at least a first predetermined gas and having a pressure below a first predetermined threshold, a cavity containing at least a second predetermined gas at a pressure below a second predetermined threshold pressure, and a cavity containing at least a third predetermined gas at a pressure above a third predetermined threshold pressure.

11. A method according to claim 1 wherein,

fabricating the at least one MEMS device comprises providing a MEMS device having at least a characteristic varying in dependence upon illumination with electromagnetic radiation, the electromagnetic radiation within a predetermined portion of the electromagnetic spectrum;

and

providing the second substrate comprises providing a material having a predetermined transmission characteristic for the predetermined portion of the electromagnetic spectrum.

12. A method according to claim 1 wherein,

fabricating the at least one MEMS device comprises providing a MEMS device having at least a characteristic varying in dependence upon an aspect of an environment external to the cavity formed by the first substrate and the at least one recess.

13. A method according to claim 1 wherein,

the substrate is a silicon substrate with integrated CMOS electronics.

14. A method comprising:

providing a substrate;

fabricating within the substrate at least one via, the at least one via comprising at least one etched feature and providing at least a first opening in a first surface of the substrate and a second opening in a second surface of the substrate;

filling a first predetermined portion of the via with a first material; and

filling a second predetermined portion of the via with a filler material.

15. A method according to claim 14 wherein,

at least one of the first material and the filler material is selected from the group comprising silicon, silicon dioxide, silicon nitride, silicon oxynitride, carbon, aluminum oxide, and silicon carbide.

16. A method according to claim 14 wherein,

at least one of the first material and the filler material is at least one of a polymer, a metal, a material exhibiting piezoelectric properties, and a material exhibiting piezoresistive properties.

17. A method according to claim 14 wherein,

the filler material is a material filling a predetermined region around a predetermined portion of the first surface of the substrate containing the at least one via.

18. A method according to claim 14 further comprising;

fabricating at least one MEMS device directly onto the substrate, the at least one MEMS device comprising at least one structural layer and fabricated with a maximum temperature exposure to the substrate of at least one of 250°

C. and 350°

C.

19. A method according to claim 18 wherein,

the structural layer is selected from the group comprising silicon, silicon dioxide, silicon nitride, silicon oxynitride, carbon, aluminum oxide, and silicon carbide.

20. A method according to claim 18 wherein,

the structural layer is at least one of a material exhibiting piezoelectric properties and a material sensitive to an aspect of the environment external to the at least one MEMS device.

21. A method comprising:

providing a substrate;

fabricating a recess within the substrate, the recess comprising at least a first opening in a first surface of the substrate and having a predetermined depth from the first surface of the substrate to a second surface of the substrate; and

filling a predetermined portion of the recess with a filler material.

22. A method according to claim 21 wherein,

the filler material is selected from the group comprising silicon, silicon dioxide, silicon nitride, silicon oxynitride, carbon, aluminum oxide, and silicon carbide.

23. A method according to claim 21 wherein,

the recess further comprises at least one via, each via having a first aperture at the predetermined depth of the recess and a second aperture at the second surface of the substrate.

24. A method according to claim 21 wherein,

filling a predetermined portion of the recess with the filler material comprises providing at least a channel within the filler material, each channel substantially parallel to at least one of the first surface and the second surface of the substrate.

25. A method according to claim 21 wherein,

the substrate is a silicon substrate with integrated CMOS electronics.

26. A method comprising:

providing a substrate, the substrate comprising at least a first surface, a second surface, and at least one CMOS electronic circuit integrated onto the second surface;

fabricating at least one via in the substrate, the at least one via comprising at least a first opening in the first surface of the substrate, a second opening in the second surface of the substrate and a plurality of side walls;

providing a metallization to at least one sidewall of the plurality of sidewalls of the at least one via;

filling a first predetermined portion of the at least one via with a filler material;

providing at least one electrical contact pad on the first surface of the substrate, the contact pad electrically connected to the at least one via;

fabricating at least a MEMS device onto the second surface of the substrate, the at least one MEMS device fabricated with a low temperature MEMS process incorporating at least one structural layer and having a maximum temperature exposure to the substrate of at least one of 250°

C. and 350°

C.; and

electrically interconnecting the at least one via, the at least one MEMS device, and the at least one CMOS electronic circuit according to a predetermined relationship.

27. A method according to claim 26 wherein,

the filler material is selected from the group comprising silicon, silicon dioxide, silicon nitride, silicon oxynitride, carbon, aluminum oxide, and silicon carbide.

28. A method according to claim 26 wherein,

the filler material is at least one of a polymer at least one of a polymer, a metal, a material exhibiting piezoelectric properties, and a material exhibiting piezoresistive properties.

29. A method according to claim 26 further comprising;

providing a cover, the cover comprising at least a third surface and a fourth surface;

fabricating at least one recess within the third surface of the cover and having a predetermined depth from the third surface towards the fourth surface of the cover;

processing a first predetermined portion of the second surface of the substrate and a first predetermined portion of the third surface of the cover; and

bonding the first predetermined portion of the second surface of the substrate and the first predetermined portion of the third surface of the cover together within a controlled environment.

30. A method according to claim 29 wherein,

bonding the first predetermined portion of the second surface of the substrate and first predetermined portion of the third surface of the cover together results in the formation of at least one of a seal, an hermetic seal, and at least one cavity, the at least one cavity positioned with respect to at least one of the at least one MEMS device and the at least one CMOS electronic circuit.

31. A method according to claim 29 wherein;

bonding the first predetermined portion of the second surface of the substrate and first predetermined portion of the third surface of cover substrate together within the controlled environment results in at least one cavity, the at least one cavity containing at least a first predetermined gas and having a pressure below a first predetermined threshold, a cavity containing at least a second predetermined gas at a pressure below a second predetermined threshold pressure, and a cavity containing at least a third predetermined gas at a pressure above a third predetermined threshold pressure.

32. A method according to claim 29 wherein,

fabricating the at least one recess further comprises depositing a getter material within the recess.

33. A method according to claim 26 wherein,

filling the at least one via with the filler material further comprises at least one of forming at least one channel within the ceramic material and depositing at least a metal to fill a second predetermined portion of the at least one via.