METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES

• US 20110027941A1
• Filed: 08/12/2010
• Published: 02/03/2011
• Est. Priority Date: 07/02/2009
• Status: Active Grant

• Current Assignee: AMF-Nano Corporation
• Original Assignee: Advanced Microfab, LLC
• Inventors: Chalil, Joseph M., Choksi, Nishit A., Kumar, G. Krishna
• Granted Patent: US 8,101,458 B2
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0728 Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence

Abstract

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step to release the mechanical layer on the prefabricated mems/nems chips; positioning protective cap to package the integrated device over the mems/nems device area on the pre-fabricated chips.

Claims

1. A method of forming a Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:

providing a semiconductor substrate selected from pre fabricated CMOS circuits, MEMS and NEMS materials on a front side and a polished backside area available for post-CMOS, micro/nano fabrication with through substrate conductive vias and the prefabricated MEMS or NEMS materials having conductive structural and dielectric layers;

forming at least one opening in the polished backside of the semiconductor substrate including protecting the front-side;

applying at least one filler material in the at least one opening on the semiconductor substrate;

positioning at least one prefabricated MEMS, NEMS or CMOS chip on the filler material, the chip including a front face and a bare back face with the filler material enabling planarization of all the corners of the chip to the substrate;

forming at least one metallization layer connecting the through substrate conductive vias to the at least one chip;

performing at least one micro/nano fabrication etching step to release the MEMS/NEMS structural layer on the front side.

2. The method of claim 1, wherein the MEMS/NEMS materials include structures selected from:

accelerometers, resonators, micro-gyroscopes, microphones, micro-bolometers, transducers involving chemical and biological properties, optical sensors, mechanical sensors, radiation sensors, thermal sensors, capacitive sensors, rotation sensors, strain sensors, magnetic and electromagnetic sensors, flow sensors, and sensors for micro-fluidic chemical properties of liquids and gases.

3. The method of claim 1, wherein the structural layer comprises polysilicon with the portion of the conductive area being doped and annealed.

4. The method of claim 1, wherein the opening in the semiconductor substrate is formed by etching with Deep Reactive Ion Etching (DRIE).

5. The method of claim 1, wherein the filler layer is selected from epoxies, polyimides, SU8, and polymers.

6. The method of claim 1, wherein the at least one chip is selected from:

CMOS integrated circuits, electronics, amplifier dies, analog to digital converters.

7. The method of claim 1, wherein the metallization layer is selected from aluminum, titanium, chrome, gold or platinum or a combination of the same that can be evaporated, sputtered or electroplated.

8. The method of claim 1, wherein the micro/nano fabrication etching step is selected from wet, dry, isotropic, and anisotropic etching.

9. A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:

providing a semiconductor substrate with pre-fabricated CMOS circuits on a front side and a polished back-side with through substrate conductive vias;

forming at least one opening in the polished backside of the semiconductor substrate including protecting the front-side;

applying at least one filler material in the at least one opening on the semiconductor substrate;

positioning at least one MEMS, NEMS chips with pre-fabricated structural and dielectric layers or CMOS chips on the filler material, the chip including a front face and a bare back face with the filler material enabling planarization of all the corners of the chip to the substrate;

forming at least one metallization layer connecting the through substrate conductive vias to the at least one chip;

performing at least one micro/nano fabrication etching step to release the structural on the prefabricated MEMS/NEMS chips;

positioning a protective cap to package the integrated device over the MEMS/NEMS device area on the pre-fabricated chips.

10. The method of claim 9, wherein the opening in the semiconductor substrate is formed by etching with Deep Reactive Ion Etching (DRIE).

11. The method of claim 9, wherein the structural layer comprises polysilicon with the portion of the conductive area being doped and annealed.

12. The method of claim 9, wherein the planarization layer is selected from oxides, nitrides, glass, quartz, and polymers.

13. The method of claim 9, wherein the prefabricated chip is selected from:

CMOS integrated circuits, electronics, amplifiers, and Analog to Digital converters.

14. The method of claim 9 wherein the MEMS/NEMS materials include structures selected from:

accelerometers, resonators, micro-gyroscopes, microphones, micro-bolometers, transducers involving chemical and biological properties, optical sensors, mechanical sensors, radiation sensors, thermal sensors, capacitive sensors, rotation sensors, strain sensors, magnetic and electromagnetic sensors, flow sensors, and sensors for micro-fluidic chemical properties of liquids and gases.

15. The method of claim 9, wherein the metallization layer is selected from aluminum, titanium, chrome, gold or platinum or a combination of the same that can be evaporated, sputtered or electroplated.