Method of Fabricating a Device Using Low Temperature Anneal Processes, a Device and Design Structure

• US 20110027956A1
• Filed: 07/29/2009
• Published: 02/03/2011
• Est. Priority Date: 07/29/2009
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: NARASIMHA, Shreesh, ONTALUS, Viorel, NUMMY, Karen A., DOMENICUCCI, Anthony G., WANG, Yun-Yu, KANE, Terence L.
• Granted Patent: US 8,236,709 B2
• Time in Patent Office: Days
• US Class Current: 438/301
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region

Abstract

A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Claims

1. A method of manufacturing a device, comprising:

forming a stress liner over a gate structure;

subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force;

stripping the stress liner from the gate structure; and

performing an activation anneal on the gate structure.

2. The method of claim 1, wherein the low temperature anneal process is about below 650°

C.

3. The method of claim 1, wherein the low temperature anneal process is between about 550°

C. to about 650°

C.

4. The method of claim 1, wherein the forming a stress liner is depositing SiN on the gate structure.

5. The method of claim 1, wherein the activation anneal is a high temperature anneal.

6. The method of claim 5, wherein the high temperature anneal is in a range of about 900°

C. to about 1100°

C.

7. The method of claim 1, wherein the activation anneal is performed after the stripping.

8. The method of claim 1, wherein the activation anneal is performed at a temperature higher than the low temperature anneal process.

9. The method of claim 1, wherein the gate structure includes a spacer and a sidewall formed over a polysilicon material.

10. The method of claim 1, further comprising implanting extension regions and doping source and drain regions in a wafer under a portion of the stress liner.

11. A method of manufacturing a logic NFET, comprising:

forming a gate structure on a wafer;

depositing a stress material over the gate structure;

subjecting the gate structure and stress liner to a low temperature anneal process at a first temperature;

stripping the stress liner from the gate structure; and

performing an activation anneal at a second temperature higher than the first temperature.

12. The method of claim 11, wherein the first temperature process is at about below 650°

C.

13. The method of claim 11, wherein the first temperature is between about 550°

C. to about 650°

C.

14. The method of claim 11, wherein forming a stress material is depositing SiN.

15. The method of claim 11, wherein the activation is performed after the stress material is stripped.

16. The method of claim 15, wherein the second temperature is about 900°

C. to 1100°

C.

17. A method of forming an NFET device, comprising:

forming a gate structure on a wafer;

depositing a stress material on the gate structure and portions of the wafer;

subjecting the stress material, gate structure and wafer to a low temperature anneal in a range of about 550°

C. to about 650°

C. to form a stacking force under the gate structure;

stripping the stress material from the gate structure and the portions of the wafer; and

subjecting the gate structure and wafer to an activation anneal, which is at a temperature higher than the low temperature anneal.

18. The method of claim 17, wherein the activation anneal is performed after the stripping.

19. The method of claim 17, wherein the activation anneal is a high temperature anneal that is performed at a temperature of about 900°

C. to 1100°

C.

20. The method of claim 17, wherein the stress material is SiN.

21. The method of claim 17, wherein the stripping is performed prior to the activation anneal.

22. A method in a computer-aided design system for generating a functional design model of a logic NFET device, the method comprising:

generating a functional representation of a gate structure on a wafer;

generating a functional representation of a stress material on the gate structure;

generating a functional representation of a low temperature anneal process in a range of about 550°

C. to about 650°

C. on the stress material;

generating a functional representation of the stress material being stripped from the gate structure; and

generating a functional representation of the gate structure being subjected to an activation anneal after the stress material is stripped, the activation anneal is at a temperature higher than the low temperature anneal.

23. The method of claim 22, wherein the functional design model comprises a netlist.

24. The method of claim 22, wherein the functional design model resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

25. The method of claim 22, wherein the functional design model resides in a programmable gate array.