METHOD OF FORMING LED STRUCTURES

• US 20110027973A1
• Filed: 07/23/2010
• Published: 02/03/2011
• Est. Priority Date: 07/31/2009
• Status: Abandoned Application

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Kryliouk, Olga, Su, Jie
• Application Number:
  US12/842,883
• Publication Number:
  US 20110027973A1
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: C23C 16/481 by radiant heating of the substrate
• CPC Class Codes: C23C 16/54 Apparatus specially adapted for continuous coating
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02455 Group 13/15 materials
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction

Abstract

One embodiment of fabricating a p-down light emitting diode (LED) structure comprises depositing a high crystal quality p type contact layer, depositing an active region on top of the p type contact layer, and depositing an n type contact layer on top of the active region using a hydride vapor phase epitaxy (HVPE) process. The high crystal quality p type contact layer is deposited at high temperature to ensure the high crystal quality of the p type film. The n type contact layer is formed on top of the active region in a HVPE chamber at a low temperature to prevent thermal damage to the quantum wells in the active region below the n type contact layer. The processing chamber used to form the p type contact layer is a separate processing chamber than the processing chamber used to form the n type contact layer.

Claims

1. A method of fabricating a semiconductor device comprising:

providing a substrate;

depositing a p type contact layer on the substrate at a high deposition temperature in a first processing chamber;

depositing an active region on top of the p type contact layer; and

depositing an n type contact layer on top of the active region at a low deposition temperature using a hydride vapor phase epitaxy (HVPE) process in a second processing chamber.

2. The method of claim 1, wherein the first processing chamber and the second processing chamber are processing chambers on a cluster tool having one or more processing chambers.

3. The method of claim 2, further comprising transferring the substrate between the processing chambers of the cluster tool without breaking vacuum.

4. The method of claim 1, wherein the substrate is selected from the group consisting of a sapphire substrate, a silicon carbide substrate, a silicon on diamond substrate, a quartz substrate, a glass substrate, a zinc oxide substrate, a magnesium oxide substrate, a lithium a gallium oxide substrate, and a lithium aluminum oxide substrate.

5. The method of claim 1, wherein the high deposition temperature is greater than 1000°

C.

6. The method of claim 1, wherein the low deposition temperature is less than 950°

C.

7. The method of claim 1, wherein the p type contact layer is a Group III-Nitride doped with a p type dopant.

8. The method of claim 7, wherein the p type dopant comprises an element having at least two valence electrons.

9. The method of claim 8, wherein the p type dopant is selected from the group consisting of Mg, Be, Ca, and Sr.

10. The method of claim 1, wherein the n type contact layer is a Group III-Nitride doped with an n type dopant.

11. The method of claim 10, wherein the n type dopant is selected from the group consisting of Si, Ge, Sn, and Pb.

12. The method of claim 1, further comprising depositing a buffer layer on top of the substrate.

13. The method of claim 1, wherein the buffer layer is an undoped GaN film.

14. A method of fabricating a semiconductor device comprising:

providing a substrate;

depositing a n type contact layer;

depositing an active region;

depositing a p type contact layer using a hydride vapor phase epitaxy (HVPE) process;

depositing a p+ layer using the HVPE process in a first processing chamber, wherein the p+ layer is in contact with the p type contact layer creating an abrupt p/p+ doping profile;

depositing an n+ layer in a second processing chamber, wherein the n+ layer is in contact with the p+ layer creating an abrupt n+/p+ doping profile; and

depositing an n type tunnel junction contact layer.

15. The method of claim 14, wherein the first processing chamber and the second processing chamber are processing chamber on a cluster tool having one or more processing chambers.

16. The method of claim 15, further comprising transferring the substrate between the processing chambers of the cluster tool without breaking vacuum.

17. The method of claim 14, wherein the substrate is selected from the group consisting of a sapphire substrate, a silicon carbide substrate, a silicon on diamond substrate, a quartz substrate, a glass substrate, a zinc oxide substrate, a magnesium oxide substrate, a lithium gallium oxide substrate, and a lithium aluminum oxide substrate.

18. The method of claim 14, wherein the n type contact layer is deposited on top the substrate, the active region is deposited on top of the n type contact layer, the p type contact layer is deposited on top of the active region, the p+ layer is deposited on top of the p type contact layer, the n+ layer is deposited on top of the p+ layer, and the n type tunnel junction contact layer is deposited on top of the n+ layer.

19. The method of claim 14, wherein the n type tunnel junction contact layer is deposited on top of the substrate, the n+ layer is deposited on top of the n type tunnel junction contact layer, the p+ layer is deposited on top of the n+ layer, the p type contact layer is deposited on top of the p+ layer, the active region is deposited on top of the p type contact layer, the n type contact layer is deposited on top of the active region.

20. The method of claim 14, wherein the n+ layer and the p+ layer are doped to a conductivity level greater 1×

10¹⁹ atoms/cm³.

21. The method of claim 14, wherein the n+ layer and the p+ layer are formed to a thickness between 1.0 nanometers and 20.0 nanometers.

22. The method of claim 14, wherein the p+ layer is a Group III-Nitride doped with a p type dopant.

23. The method of claim 22, wherein the p type dopant comprises an element having at least two valence electrons.

24. The method of claim 23, wherein the p type dopant is selected from the group consisting of Mg, Be, Ca, and Sr.

25. The method of claim 14, wherein the n type tunnel junction contact layer is a Group III-Nitride doped with an n type dopant.

26. The method of claim 25, wherein the n type dopant is selected from the group consisting of Si, Ge, Sn, and Pb.

27. The method of claim 14, wherein the p type contact layer is a Group III-Nitride doped with a p type dopant.

28. The method of claim 27, wherein the p type dopant comprises an element having at least two valence electrons.

29. The method of claim 28, wherein the p type dopant is selected from the group consisting of Mg, Be, Ca, and Sr.