COMPUTING CORE APPLICATION ACCESS UTILIZING DISPERSED STORAGE

• US 20110029743A1
• Filed: 04/06/2010
• Published: 02/03/2011
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Cleversafe Incorporated (International Business Machines Corporation)
• Inventors: GRUBE, GARY W., MARKISON, TIMOTHY W.
• Granted Patent: US 8,448,016 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computing core application access method begins by a processing module detecting selection of an application. The method continues with at least one of a memory controller and the processing module addressing a distributed application memory to retrieve a plurality of error coded program data slices and a plurality of error coded configuration data slices. The method continues with the at least one of a memory controller and the processing module reconstructing a data segment of a program from the plurality of error coded program data slices using an error coding dispersal function. The method continues with the at least one of a memory controller and the processing module reconstructing a data segment of a configuration information from the plurality of error coded configuration data slices using a second error coding dispersal function. The method continues with the at least one of a memory controller and the processing module storing the data segment of the program and the data segment of the configuration information in a main memory of the computing core.

Claims

1. A method for execution by a computing core, the method comprises:

detecting selection of an application;

addressing a distributed application memory to retrieve a plurality of error coded program data slices and a plurality of error coded configuration data slices;

reconstructing a data segment of a program from the plurality of error coded program data slices using an error coding dispersal function;

reconstructing a data segment of configuration information from the plurality of error coded configuration data slices using a second error coding dispersal function; and

storing the data segment of the program and the data segment of the configuration information in main memory of the computing core.

2. The method of claim 1, wherein the second error coding dispersal function is substantially the same as the error coding dispersal function.

3. The method of claim 1, wherein the addressing of the distributed application memory further comprises:

addressing a first memory of the distributed application memory to retrieve the plurality of error coded program data slices; and

addressing a second memory of the distributed application memory to retrieve the plurality of error coded configuration data slices.

4. In the method of claim 1 further comprises:

detecting a change in the configuration information;

when a change is detected in the configuration information, updating the configuration information to produce updated configuration information; and

facilitating storage of the updated configuration information in the distributed application memory.

5. In the method of claim 1, the addressing of the distributed application memory comprises one or more of:

addressing at least one of a plurality of local non-volatile memory devices;

addressing at least one of a plurality of local area network (LAN) memory devices; and

addressing at least one of a plurality of wide area network (WAN) memory devices.

6. A method for execution by a computer core, the method comprises:

detecting closing of an application;

reading a data segment of configuration information of the application from main memory of the computing core;

generating, when enabled, a plurality of error coded configuration data slices using a second error coding dispersal function from the data segment; and

addressing a distributed application memory for storage of the plurality of error coded configuration data slices.

7. In the method of claim 6 further comprises:

determining whether the configuration information has changed; and

when the configuration information has changed, enabling the generating of the plurality of error coded configuration data slices.

8. In the method of claim 6, the addressing of the distributed application memory comprises one or more of:

addressing at least one of a plurality of local non-volatile memory devices;

addressing at least one of a plurality of LAN memory devices; and

addressing at least one of a plurality of WAN memory devices.

9. A computing core comprises:

a processing module;

main memory; and

a memory controller, wherein;

the processing module detects selection of an application;

at least one of the memory controller and the processing module addresses a distributed application memory to retrieve a plurality of error coded program data slices and a plurality of error coded configuration data slices;

the at least one of the memory controller and the processing module reconstructs a data segment of a program from the plurality of error coded program data slices using an error coding dispersal function;

the at least one of the memory controller and the processing module reconstructs a data segment of configuration information from the plurality of error coded configuration data slices using a second error coding dispersal function; and

the main memory stores the data segment of the program and the data segment of the configuration information.

10. In the computing core of claim 9, wherein the second error coding dispersal function is substantially the same as the error coding dispersal function.

11. In the computing core of claim 9, wherein the at least one of the memory controller and the processing module addresses the distributed application memory further comprises:

addressing a first memory of the distributed application memory to retrieve the plurality of error coded program data slices; and

addressing a second memory of the distributed application memory to retrieve the plurality of error coded configuration data slices.

12. In the computing core of claim 9 further comprises:

detecting, by the at least one of the memory controller and the processing module, a change in configuration information;

when a change is detected in configuration information, by the at least one of the memory controller and the processing module, updating, by the at least one of the memory controller and the processing module, the configuration information to produce updated configuration information; and

facilitating, by the at least one of the memory controller and the processing module, storage of the updated configuration information.

13. In the computing core of claim 9, wherein the at least one of the memory controller and the processing module address the distributed application memory by one or more of:

addressing at least one of a plurality of local non-volatile memory devices;

addressing at least one of a plurality of LAN memory devices; and

addressing at least one of a plurality of WAN memory devices.

14. A computing core comprises:

a processing module;

main memory; and

a memory controller, wherein;

the processing module detects closing of an application;

at least one of the memory controller and the processing module reads a data segment of configuration information of the application from the main memory;

when enabled, the at least one of the memory controller and the processing module generates a plurality of error coded configuration data slices using a second error coding dispersal function from the data segment; and

the at least one of the memory controller and the processing module addresses a distributed application memory for storage of the plurality of error coded configuration data slices.

15. In the computing core of claim 14, wherein the at least one of the memory controller and the processing module generates the plurality of error coded configuration data slices further comprises:

determining whether the configuration information has changed; and

when the configuration information has changed, enabling the generating of the plurality of error coded configuration data slices.

16. In the computing core of claim 14, the at least one of the memory controller and the processing module addresses the distributed application memory comprising one or more of:

addressing at least one of a plurality of local non-volatile memory devices;

addressing at least one of a plurality of LAN memory devices; and

addressing at least one of a plurality of WAN memory devices.