SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110031491A1
• Filed: 07/29/2010
• Published: 02/10/2011
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KUWABARA, Hideaki, HOSOBA, Miyuki, YAMAZAKI, Shunpei, SAKATA, Junichiro
• Granted Patent: US 8,384,079 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/167 by electrophoresis
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/344 based on particles moving in a fluid or in a gas, e.g. electrophoretic devices electrophoretic devices per se G02F1/167
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Claims

1. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer including a channel formation region overlapping with the gate electrode layer;

an oxide insulating layer over the gate electrode layer with the oxide semiconductor layer interposed therebetween, the oxide insulating layer being in contact with a first region of the oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and

an insulating layer over the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises a second region in contact with the source electrode layer or the drain electrode layer, and a third region in contact with the insulating layer, and

wherein the third region is located between the first region and the second region.

3. The semiconductor device according to claim 1, wherein an upper surface and a side surface of the oxide insulating layer overlapping with the channel formation region are covered with the insulating layer.

5. The semiconductor device according to claim 1, wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

7. The semiconductor device according to claim 1, wherein the insulating layer is a silicon nitride film or an aluminum nitride film.

9. The semiconductor device according to claim 1, further comprising a second oxide insulating layer above and in contact with the gate insulating layer.

11. The semiconductor device according to claim 9, wherein a peripheral portion of the oxide semiconductor layer is interposed between the gate insulating layer and the second oxide insulating layer.

13. The semiconductor device according to claim 9, wherein the second oxide insulating layer is thicker than the gate insulating layer.

15. The semiconductor device according to claim 9,

wherein a stacked layer, formed of the gate insulating layer and the second oxide insulating layer, is interposed between a first electrically conductive layer and a second electrically conductive layer;

wherein the first electrically conductive layer is located below the stacked layer and formed from a same layer as the gate electrode layer; and

wherein the second electrically conductive layer is located over the stacked layer and formed from a same layer as the source electrode layer.

17. The semiconductor device according to claim 1, further comprising:

a protective insulating layer over the insulating layer;

a planarizing insulating layer over the protective insulating layer; and

a terminal electrode over the protective insulating layer and in contact with an electrically conductive wiring made from a same layer as the source electrode layer.

19. The semiconductor device according to claim 17, wherein the terminal electrode is in direct contact with an upper surface of the protective insulating layer.

21. An electronic device incorporating the semiconductor device according to claim 1.

2. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

an oxide insulating layer over the oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and

an insulating layer over the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer comprises a first region in contact with the oxide insulating layer, a second region in contact with the source electrode layer or the drain electrode layer, and a third region in contact with the insulating layer,

wherein, in the first region, a channel formation region overlaps with the gate electrode layer with the gate insulating layer interposed therebetween, and

wherein the third region is located between the channel formation region and the second region.

4. The semiconductor device according to claim 2, wherein an upper surface and a side surface of the oxide insulating layer overlapping with the channel formation region are covered with the insulating layer.

6. The semiconductor device according to claim 2, wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

8. The semiconductor device according to claim 2, wherein the insulating layer is a silicon nitride film or an aluminum nitride film.

10. The semiconductor device according to claim 2, further comprising a second oxide insulating layer above and in contact with the gate insulating layer.

12. The semiconductor device according to claim 10, wherein a peripheral portion of the oxide semiconductor layer is interposed between the gate insulating layer and the second oxide insulating layer.

14. The semiconductor device according to claim 10, wherein the second oxide insulating layer is thicker than the gate insulating layer.

16. The semiconductor device according to claim 10,

wherein a stacked layer, formed of the gate insulating layer and the second oxide insulating layer, is interposed between a first electrically conductive layer and a second electrically conductive layer;

wherein the first electrically conductive layer is located below the stacked layer and formed from a same layer as the gate electrode layer; and

wherein the second electrically conductive layer is located over the stacked layer and formed from a same layer as the source electrode layer.

18. The semiconductor device according to claim 2, further comprising:

a protective insulating layer over the insulating layer;

a planarizing insulating layer over the protective insulating layer; and

a terminal electrode over the protective insulating layer and in contact with an electrically conductive wiring made from a same layer as the source electrode layer.

20. The semiconductor device according to claim 18, wherein the terminal electrode is in direct contact with an upper surface of the protective insulating layer.

22. An electronic device incorporating the semiconductor device according to claim 2.

23. A method of forming a semiconductor device, comprising the steps of:

forming a gate insulating layer over a gate electrode layer;

forming an oxide semiconductor layer over the gate insulating layer;

dehydrating or dehydrogenating the oxide semiconductor layer;

forming an oxide insulating layer being in contact with part of the oxide semiconductor layer and covering a peripheral portion and a side surface of the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer over the oxide insulating layer; and

forming an insulating layer in contact with the oxide insulating layer, the source electrode layer, the drain electrode layer, and the oxide semiconductor layer,

wherein the oxide semiconductor layer is prevented from being exposed to air between the step of dehydrating or dehydrogenating the oxide semiconductor layer and the step of forming the oxide insulating layer, so as to prevent water or hydrogen contamination.

24. The method of forming a semiconductor device according to claim 23, wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

25. The method of forming a semiconductor device according to claim 23, wherein the insulating layer is a silicon oxide film or an aluminum oxide film.

26. The method of forming a semiconductor device according to claim 23, further comprising the steps of:

forming a first electrically conductive layer from a same layer as the gate electrode layer;

forming a second oxide insulating layer above and in contact with the gate insulating layer; and

forming a second electrically conductive layer from a same layer as the source electrode layer, over the second oxide insulating layer.

27. The method of forming a semiconductor device according to claim 23, further comprising the steps of:

forming a first electrically conductive layer from a same layer as the source electrode layer;

forming a protective insulating layer above and in contact with the gate insulating layer;

forming a planarizing insulating layer over the protective insulating layer; and

forming a second electrically conductive layer above and in direct contact with an upper surface of the protective insulating layer, and in contact with the first electrically conductive layer.