STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC

• US 20110031554A1
• Filed: 08/04/2009
• Published: 02/10/2011
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi, Fang, Sunfei, Wang, Yanfeng, Maciejewski, Edward P., Liang, Qingqing, Greene, Brian J.
• Granted Patent: US 8,173,531 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.

Claims

1. A method of fabricating a semiconductor structure comprising:

providing at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and

forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500°

C. in a nitrogen-containing ambient.

2. The method of claim 1 wherein said providing the at least one patterned gate stack includes providing a patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor, wherein the patterned threshold voltage adjusting layer is a pFET threshold voltage adjusting material or an nFET threshold voltage material.

3. The method of claim 2 wherein said threshold voltage adjusting material is a pFET threshold voltage adjusting material, said pFET threshold adjusting material includes Al, Al₂O₃, Ge, GeO₂, Ta, Ta₂O₅, Ti, or TiO₂.

4. The method of claim 2 wherein said threshold voltage adjusting material is an nFET threshold voltage adjusting material, said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material.

5. The method of claim 1 further comprising forming an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of the at least one patterned gate stack, wherein said forming the embedded semiconductor material is performed before the forming the conformal nitride-containing liner or after forming the conformal nitride-containing liner.

6. The method of claim 5 wherein said embedded semiconductor material is formed prior to forming the conformal nitride-containing liner, and said conformal nitride-containing liner is present only on exposed sidewalls of the patterned gate dielectric material.

7. A method of fabricating a CMOS structure comprising:

providing a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, said first patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, and a patterned gate conductor and said second patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, and a patterned gate conductor; and

forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material in both device regions, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500°

C. in a nitrogen-containing ambient.

8. The method of claim 7 further comprising providing a patterned first threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor in the first patterned gate stack, and a patterned second threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor in the second patterned gate stack, wherein said first patterned threshold voltage layer is either a pFET threshold voltage adjusting material or an nFET threshold voltage material, while the second patterned threshold voltage layer is the other of a pFET threshold voltage adjusting material or an nFET threshold voltage material not used as the first patterned threshold voltage layer.

9. The method of claim 8 wherein said pFET threshold adjusting material includes Al, Al₂O₃, Ge, GeO₂, Ta, Ta₂O₅, Ti, or TiO₂.

10. The method of claim 8 wherein said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material.

11. The method of claim 7 further comprising forming an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of one of the patterned gate stacks, wherein said forming the embedded semiconductor material is performed before the forming the conformal nitride-containing liner or after forming the conformal nitride-containing liner.

12. The method of claim 11 wherein said embedded semiconductor material is formed prior to forming the conformal nitride-containing liner, and said conformal nitride-containing liner is present only on exposed sidewalls of the patterned gate dielectric material.

13. A method of fabricating a CMOS structure comprising:

providing a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, said first patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor and said second patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor;

forming an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of one of the patterned gate stacks;

selectively exposing a sidewall of said patterned gate dielectric material of each of said patterned gate stacks; and

forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material in both device regions, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500°

C in a nitrogen-containing ambient.

14. The method of claim 13 further comprising providing a patterned first threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor in the first patterned gate stack, and a patterned second threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor in the second patterned gate stack, wherein said first patterned threshold voltage layer is either a pFET threshold voltage adjusting material or an nFET threshold voltage material, while the second patterned threshold voltage layer is the other of a pFET threshold voltage adjusting material or an nFET threshold voltage material not used as the first patterned threshold voltage layer.

15. The method of claim 14 wherein said pFET threshold adjusting material includes Al, Al₂O₃, Ge, GeO₂, Ta, Ta₂O₅, Ti, or TiO₂.

16. The method of claim 14 wherein said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material.

17. The method of claim 13 further comprising forming another conformal nitride-containing liner on exposed sidewalls of the patterned gate stack in both device regions, wherein said forming the another conformal nitride-containing liner is performed at a temperature of less than 500°

C. in a nitrogen-containing ambient.

18. A semiconductor structure comprising:

at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and

a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material, said conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm.

19. The semiconductor structure of claim 18 further including a patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor, wherein said patterned threshold voltage adjusting layer includes a pFET threshold voltage adjusting material selected from Al, Al₂O₃, Ge, GeO₂, Ta, Ta₂O₅, Ti, and TiO₂.

20. The semiconductor structure of claim 18 further including a patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor, wherein said patterned threshold voltage adjusting layer is an nFET threshold voltage adjusting material, said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material.

21. The semiconductor structure of claim 18 further comprising an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of the at least one patterned gate stacks.

22. A semiconductor structure comprising:

a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, wherein said first patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor and said second patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and

a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material in both device regions, the conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm.

23. The semiconductor structure of claim 22 further comprising a first patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor in the first patterned gate stack and a second patterned threshold voltage adjusting layer between the patterned gate dielectric and the patterned gate conductor in the second patterned gate stack wherein one of the first or second patterned threshold voltage adjusting layers is a pFET threshold voltage adjusting material selected from Al, Al₂O₃, Ge, GeO₂, Ta, Ta₂O₅, Ti, and TiO₂.

24. The semiconductor structure of claim 23 wherein the other of said first or second patterned threshold voltage adjusting layers not including a pFET threshold voltage adjusting material is an nFET threshold voltage adjusting material, said nFET threshold adjusting material includes a rare earth metal-containing material or an alkaline earth metal-containing material.

25. The semiconductor structure of claim 22 further comprising an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of one of the patterned gate stacks.