STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC
First Claim
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1. A method of fabricating a semiconductor structure comprising:
- providing at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and
forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500°
C. in a nitrogen-containing ambient.
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Abstract
A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
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Citations
25 Claims
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1. A method of fabricating a semiconductor structure comprising:
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providing at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500°
C. in a nitrogen-containing ambient. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating a CMOS structure comprising:
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providing a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, said first patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, and a patterned gate conductor and said second patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide, and a patterned gate conductor; and forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material in both device regions, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500°
C. in a nitrogen-containing ambient. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method of fabricating a CMOS structure comprising:
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providing a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, said first patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor and said second patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; forming an embedded semiconductor material having a different lattice constant than the semiconductor substrate within the semiconductor substrate at a footprint of one of the patterned gate stacks; selectively exposing a sidewall of said patterned gate dielectric material of each of said patterned gate stacks; and forming a conformal nitride-containing liner on at least exposed sidewalls of the patterned gate dielectric material in both device regions, wherein said forming the conformal nitride-containing liner is performed at a temperature of less than 500°
C in a nitrogen-containing ambient. - View Dependent Claims (14, 15, 16, 17)
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18. A semiconductor structure comprising:
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at least one patterned gate stack in at least one device region of a semiconductor substrate, said at least one patterned gate stack including from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material, said conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm. - View Dependent Claims (19, 20, 21)
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22. A semiconductor structure comprising:
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a first patterned gate stack in a first device region of a semiconductor substrate, and a second patterned gate stack in a second device region of the semiconductor substrate, wherein said first patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor and said second patterned gate stack includes from bottom to top, a patterned gate dielectric material having a dielectric constant of greater than silicon oxide and a patterned gate conductor; and a conformal nitride-containing liner located on at least exposed sidewalls of the patterned gate dielectric material in both device regions, the conformal nitride-containing liner having a thickness of from 0.5 nm to 50 nm. - View Dependent Claims (23, 24, 25)
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Specification