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GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM

  • US 20110031557A1
  • Filed: 10/20/2010
  • Published: 02/10/2011
  • Est. Priority Date: 12/31/2008
  • Status: Active Grant
First Claim
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1. A method for fabricating a CMOS integrated circuit (IC), comprising:

  • providing a substrate having a semiconductor surface, said semiconductor surface having PMOS regions for PMOS devices and NMOS regions for NMOS devices;

    forming a gate dielectric layer on said PMOS regions and said NMOS regions;

    forming an original gate electrode layer on said gate dielectric;

    applying a gate masking layer on said gate electrode layer;

    etching to pattern said original gate electrode layer to simultaneously form original gate electrodes for said PMOS devices and said NMOS devices;

    forming source/drain regions for said PMOS devices and said NMOS devices;

    removing said original gate electrodes for at least one of said PMOS devices and said NMOS devices to form trenches using an etch process, wherein at least a portion of said gate dielectric layer is preserved;

    forming metal comprising replacement gates in said trenches, andcompleting fabrication of said IC.

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