GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM
First Claim
1. A method for fabricating a CMOS integrated circuit (IC), comprising:
- providing a substrate having a semiconductor surface, said semiconductor surface having PMOS regions for PMOS devices and NMOS regions for NMOS devices;
forming a gate dielectric layer on said PMOS regions and said NMOS regions;
forming an original gate electrode layer on said gate dielectric;
applying a gate masking layer on said gate electrode layer;
etching to pattern said original gate electrode layer to simultaneously form original gate electrodes for said PMOS devices and said NMOS devices;
forming source/drain regions for said PMOS devices and said NMOS devices;
removing said original gate electrodes for at least one of said PMOS devices and said NMOS devices to form trenches using an etch process, wherein at least a portion of said gate dielectric layer is preserved;
forming metal comprising replacement gates in said trenches, andcompleting fabrication of said IC.
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Abstract
A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.
11 Citations
22 Claims
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1. A method for fabricating a CMOS integrated circuit (IC), comprising:
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providing a substrate having a semiconductor surface, said semiconductor surface having PMOS regions for PMOS devices and NMOS regions for NMOS devices; forming a gate dielectric layer on said PMOS regions and said NMOS regions; forming an original gate electrode layer on said gate dielectric; applying a gate masking layer on said gate electrode layer; etching to pattern said original gate electrode layer to simultaneously form original gate electrodes for said PMOS devices and said NMOS devices; forming source/drain regions for said PMOS devices and said NMOS devices; removing said original gate electrodes for at least one of said PMOS devices and said NMOS devices to form trenches using an etch process, wherein at least a portion of said gate dielectric layer is preserved; forming metal comprising replacement gates in said trenches, and completing fabrication of said IC. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for fabricating a CMOS integrated circuit (IC), comprising:
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providing a substrate having a semiconductor surface, said semiconductor surface having PMOS regions for PMOS devices and NMOS regions for NMOS devices; forming a gate dielectric layer on said PMOS regions and said NMOS regions, wherein said gate dielectric layer comprises a high-k dielectric material having a k-value >
10;forming an original polysilicon comprising gate electrode layer on said gate dielectric; doping said original polysilicon comprising gate electrode layer in both said PMOS regions and said NMOS regions n-type to a doping level of at least 1×
1018 cm−
3;applying a gate masking layer on said original polysilicon comprising gate electrode layer; etching to pattern said original polysilicon comprising gate electrode layer to simultaneously form original gate electrodes for said PMOS devices and said NMOS devices; forming source/drain regions for said PMOS devices and said NMOS devices; depositing at least one pre-planarization dielectric layer; chemical mechanical polishing (CMP) to planarize and expose said original gate electrodes; removing said original gate electrodes for said PMOS devices and said NMOS devices to form trenches using a wet etch solution comprising at least one non-alkali hydroxide solution, wherein at least a portion of said high-k gate dielectric layer is preserved; forming metal comprising replacement gates in said trenches, and completing fabrication of said IC. - View Dependent Claims (18)
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19. An integrated circuit (IC) including at least one replacement gate MOS device, said replacement gate MOS device comprising:
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a substrate having a semiconductor surface; a gate stack on said semiconductor surface comprising a patterned metal comprising gate electrode layer over a gate dielectric layer, wherein said patterned metal comprising gate electrode layer has a top surface and said gate dielectric has a length dimension in a source-drain direction of said MOS device; a gate sidewall comprising at least one dielectric layer on a sidewall of said gate stack, and a source and a drain on opposing sides of said gate stack; wherein; (i) a position of said top surface of said patterned metal comprising gate electrode layer and a position of a top surface of said gate sidewall proximate to said patterned metal comprising gate electrode layer are within 1 nm of one another, and (ii) a length of said top of said patterned metal comprising gate electrode layer is within 0.5 nm of said length dimension of said gate dielectric layer. - View Dependent Claims (20, 21, 22)
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Specification