SEALING LAYER OF A FIELD EFFECT TRANSISTOR

• US 20110031562A1
• Filed: 04/09/2010
• Published: 02/10/2011
• Est. Priority Date: 08/07/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHEN, Ryan Chia-Jen, LIN, Jr Jung, LIN, Jih-Jse, CHEN, Chao-Cheng, LIN, Yih-Ann, LIN, Yu Chao, CHANG, Weng
• Granted Patent: US 8,258,588 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Claims

1. A gate structure of a field effect transistor comprising:

a gate electrode;

a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and

a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of an upper portion of the sealing layer on sidewalls of the gate electrode.

2. The gate structure of claim 1, wherein the sealing layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, or silicon-rich oxide.

3. The gate structure of claim 1, wherein a ratio of a minimum thickness of the lower portion to a maximum thickness of the upper portion of the sealing layer is from 0.5 to 0.9.

4. The gate structure of claim 1, wherein a maximum thickness of the upper portion of the sealing layer is in a range of between about 50 angstroms and 80 angstroms.

5. The gate structure of claim 1, wherein a minimum thickness of the lower portion of the sealing layer is in a range of between about 25 angstroms and 60 angstroms.

6. The gate structure of claim 1, wherein the gate insulator comprises a high-k dielectric material.

7. The gate structure of claim 1, wherein a third length of the footing regions of the gate insulator has an average length ranging from 25 to 60 angstroms.

8. The gate structure of claim 1, wherein a sum (TS) of a third length of the footing regions and a minimum thickness of the lower portion of the sealing layer is larger than a maximum thickness of the upper portion of the sealing layer (TU).

9. The gate structure of claim 8, wherein a difference between TS and TU is between about 5 angstroms and 10 angstroms.

10. The gate structure of claim 1, wherein the gate electrode comprises poly-silicon or metal.

11. A field effect transistor comprising:

a substrate comprising an active region;

a gate structure comprising a gate electrode and a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode;

a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of an upper portion of the sealing layer on sidewalls of the gate electrode; and

source and drain regions in the active region on opposite sides of the gate structure.

12. The field effect transistor of claim 11, wherein the sealing layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon-rich oxide.

13. The field effect transistor of claim 11, wherein a ratio of a minimum thickness of the lower portion to a maximum thickness of the upper portion of the sealing layer is between from 0.5 to 0.9.

14. The field effect transistor of claim 11, wherein a maximum thickness of the upper portion of the sealing layer is in a range of between about 50 angstroms and 80 angstroms.

15. The field effect transistor of claim 11, wherein a minimum thickness of the lower portion of the sealing layer is in a range of between about 25 angstroms and 60 angstroms.

16. The field effect transistor of claim 11, wherein the gate insulator comprises a high-k dielectric material.

17. The field effect transistor of claim 11, wherein a third length of the footing regions of the gate insulator has an average length ranging from 25 to 60 angstroms.

18. The field effect transistor of claim 11, wherein a sum (TS) of a third length of the footing regions and a minimum thickness of the lower portion of the sealing layer is larger than the thickness of the upper portion of the sealing layer (TU).

19. The field effect transistor of claim 18, wherein the difference between TS and TU is about 5 to 10 angstroms.

20. The field effect transistor of claim 11, wherein the gate electrode comprises poly-silicon or metal.