MICROMACHINED DEVICES AND FABRICATING THE SAME

• US 20110031565A1
• Filed: 08/03/2010
• Published: 02/10/2011
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bryzek, Janusz, Akkaraju, Sandeep, Acar, Cenk, Marx, David Lambe
• Granted Patent: US 8,710,599 B2
• Time in Patent Office: Days
• US Class Current: 257/417
• CPC Class Codes: G01C 19/5712 the devices involving a micromechanical structure
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: G01P 2015/082 for two degrees of freedom of movement of a single mass
• CPC Class Codes: G01P 2015/0842 the mass being of clover leaf shape
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

Micromachined devices and methods for making the devices. The device includes: a first wafer having at least one via; and a second wafer having a micro-electromechanical-systems (MEMS) layer. The first wafer is bonded to the second wafer. The via forms a closed loop when viewed in a direction normal to the top surface of the first wafer to thereby define an island electrically isolated. The method for fabricating the device includes: providing a first wafer having at least one via; bonding a second wafer having a substantially uniform thickness to the first wafer; and etching the bonded second wafer to form a micro-electromechanical-systems (MEMS) layer.

Claims

1. A method for fabricating a device, comprising:

providing a first wafer having at least one via;

bonding a second wafer having a substantially uniform thickness to the first wafer; and

etching the bonded second wafer to form a micro-electromechanical-systems (MEMS) layer.

2. A method of claim 1, wherein the MEMS layer is adapted to measure one or more of angular rates about three axes and linear accelerations about the three axes.

3. A method as recited in claim 1, further comprising:

forming a groove around a perimeter of the second wafer to isolate the MEMS layer from thermal stress.

4. A method as recited in claim 1, wherein the first wafer is silicon-silicon fusion bonded to the second wafer along a perimeter of the second wafer.

5. A method as recited in claim 1, wherein the step of bonding includes bonding an anchor of the first wafer to the second wafer.

6. A method as recited in claim 1, wherein the via forms a closed loop when viewed in a direction normal to a top surface of the first wafer to thereby define an island electrically isolated.

7. A method as recited in claim 1, further comprising:

bonding a third wafer to the second wafer.

8. A method as recited in claim 7, further comprising, after the step of bonding a third wafer:

etching a surface of the third wafer facing away from the second wafer to transfer an etch marker mask from the first wafer to the surface.

9. A method as recited in claim 8, further comprising, after the step of etching a surface:

removing a portion of the first wafer to expose the via.

10. A method as recited in claim 9, further comprising, after the step of grinding:

forming a dielectric layer over a surface of the first wafer to thereby insulate the expose via;

patterning the dielectric layer; and

forming one or more electrical contacts over the dielectric layer.

11. A method as recited in claim 7, wherein the third wafer is an ASIC wafer.

12. A method as recited in claim 1, wherein the step of providing a first wafer includes:

preparing a wafer having a stack of a first dielectric layer, a first silicon layer, a second dielectric layer, a second silicon layer, and a third dielectric layer;

removing the first dielectric layer;

etching the first silicon layer to form at least one via opening, a bottom of the opening being defined by the second dielectric layer; and

processing the etched first silicon layer to form the via.

13. A method as recited in claim 12, further comprising:

removing the second silicon layer after bonding the second wafer to the first wafer.

14. A method as recited in claim 12, further comprising:

removing the third dielectric layer before bonding the second wafer to the first wafer.

15. A method as recited in claim 12, wherein the step of processing the etched first silicon layer includes:

disposing a fourth dielectric layer over the via opening;

disposing a conductive layer over the fourth dielectric layer; and

patterning the fourth dielectric layer and the conductive layer to form the via.

16. A method as recited in claim 1, wherein the first wafer is formed of doped silicon having a resistivity equal to or less than 0.02 ohm-cm.

17. A device, comprising:

a first wafer having at least one via; and

a second wafer bonded to the first wafer and having a micro-electromechanical-systems (MEMS) layer,

wherein the via forms a closed loop when viewed in a direction normal to a top surface of the first wafer to thereby define an island electrically isolated.

18. A device of claim 17, wherein the MEMS layer is adapted to measure one or more of angular rates about three axes and linear accelerations about the three axes.

19. A device as recited in claim 17, wherein the first wafer includes a dielectric layer formed on a surface thereof and one or more contacts disposed over the dielectric layer, one of the contacts being electrically connected to the island.

20. A device as recited in claim 17, wherein the via includes a core filled with an electrically conducting material and a dielectric layer surrounding the core.

21. A device as recited in claim 20, wherein the first wafer includes a dielectric layer formed on a surface thereof and one or more contacts disposed over the dielectric layer, one of the contacts being electrically connected to the core of the via.

22. A device as recited in claim 17, wherein the first wafer includes first and second vias, the first via forming a first closed loop to define a first island, the second via forming a second closed loop surrounding the first closed loop to thereby define a second island having a ring shape and electrically insulated from the first island.

23. A device as recited in claim 22, wherein the first and second islands are respectively connected to first and second contacts, the first island being adapted to operate as a sensor and communicate a signal via the first contact, the second island being connected to a ground via the second contact.

24. A device as recited in claim 17, further comprising:

A third wafer bonded to the first and second wafers.

25. A device as recited in claim 24, further comprising:

an ACIS wafer bonded to the first wafer.

26. A device as recited in claim 17, wherein at least one of the first and second wafers includes a cavity to thereby cause portions of the first wafer to be spaced apart from the second wafer.