LEVEL SHIFTER WITH OUTPUT LATCH

• US 20110032019A1
• Filed: 08/07/2009
• Published: 02/10/2011
• Est. Priority Date: 08/07/2009
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Saether, Terje
• Granted Patent: US 8,587,359 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A level shifter for a microcontroller shifts an input voltage in a first power domain to an output voltage level consistent with a second power domain. The level shifter is enabled to shift the voltages when both power domains are operative.

Claims

1. A device comprising:

a power input to couple to a power in voltage of a first power domain;

a power output to couple to a power out voltage of a second power domain;

an input to receive a logic signal having a level consistent with the first power domain;

an output to provide a level shifted logic signal output having a level consistent with the second power domain; and

a latch operable to selectively latch the level shifted logic signal output.

2. The device of claim 1 wherein the latch comprises a cross coupled inverter.

3. The device of claim 1 and further comprising a latch switch to couple to an enable signal input such that an enable signal controls the latch switch to latch the level shifted logic signal and stop the latch from drawing current from the power out voltage.

4. The device of claim 3 wherein the latch switch comprises a pair of transistors having gates to couple to the enable signal input.

5. The device of claim 4 wherein the cross coupled inverter comprises two pairs of transistors, each transistor in each pair having gates tied together and having the pairs of gates coupled between the transistors of the other pair of transistors.

6. The device of claim 5 wherein the latch switch transistors having outputs respectively coupled to one of gates of the pairs of cross coupled inverter transistors.

7. The device of claim 1 and further comprising a voltage detection circuit coupled to second power domain to determine whether the first power domain is powered and to provide the enable signal as a function of the determination, wherein the first and second power domains are independent from each other.

8. The device of claim 1 wherein the device is coupled between a microcontroller and an input pin of the microcontroller.

9. The device of claim 8 wherein the microcontroller is a controller for a touchscreen and the input pin is to couple to an analog to digital converter of the touchscreen.

10. The device of claim 1 wherein the first power domain is an analog domain and the second power domain is a digital domain.

11. The device of claim 10 wherein the voltage of the analog domain is higher than the voltage of the digital domain.

12. A controller comprising:

a processor operating in a digital power domain, the processor to generate control signals and receive input signals from a touchscreen operating in an analog domain via a plurality of I/O pins;

each input signal I/O pin having at least one level shifter to switch the voltage level of input signals from the analog domain to the digital domain, each level shifter comprising;

an power input to couple to a power in voltage of a first power domain;

a power output to couple to a power out voltage of a second power domain independent from the first power domain;

an input to receive a logic signal having a level consistent with the first power domain;

an output to provide a level shifted logic signal output having a level consistent with the second power domain; and

a latch operable to selectively latch the level shifted logic signal output.

13. The controller of claim 12 wherein the latch comprises a cross coupled inverter.

14. The controller of claim 12 and further comprising a latch switch to couple to an enable signal input such that an enable signal controls the latch switch to latch the level shifted logic signal and stop the latch from drawing current from the power out voltage.

15. The controller of claim 14 wherein the latch switch comprises a pair of transistors having gates to couple to the enable signal input.

16. The controller of claim 15 wherein the cross coupled inverter comprises two pairs of transistors, each transistor in each pair having gates tied together and having the pairs of gates coupled between the transistors of the other pair.

17. The controller of claim 12 wherein each output signal I/O pin has at least one level shifter to switch the voltage level of input signals from the digital domain to the analog domain, each level shifter comprising:

a power input to couple to a power in voltage of the second power domain;

a power output to couple to a power out voltage of the first power domain independent from the second power domain;

an input to receive a logic signal having a level consistent with the second power domain;

an output to provide a level shifted logic signal output having a level consistent with the first power domain; and

a latch operable to selectively latch the level shifted logic signal output.

18. The controller of claim 12 and further comprising a voltage detection circuit coupled to second power domain to determine whether the first power domain is powered and to provide the enable signal as a function of the determination.

19. A method comprising:

shifting input voltages from a first power domain to a second power domain via a level shifter having an input corresponding to voltages in the first power domain and an output having an output corresponding to voltages in the second power domain;

detecting that one of the first and second power domains is off via a voltage detection circuit;

latching an output of the level shifter responsive to detecting that one of the first and second power domains is off; and

disabling the level shifter responsive to detecting that one of the first and second power domains is off.

20. The method of claim 19 and further comprising:

transferring information from the first power domain to the second power domain and saving the information in the second power domain.