SYSTEMS AND METHODS FOR SATURATION DETECTION AND CORECTION IN A POWER CONTROL LOOP

• US 20110032030A1
• Filed: 07/03/2008
• Published: 02/10/2011
• Est. Priority Date: 07/05/2007
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Ripley, David S, Phillips, Kerry B
• Granted Patent: US 8,188,793 B2
• Time in Patent Office: Days
• US Class Current: 330/96
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 2200/66 Clipping circuitry being present in an amplifier, i.e. the shape of the signal being modified
• CPC Class Codes: H03F 3/20 Power amplifiers, e.g. Class B amplifiers, Class C amplifiers H03F3/26 - H03F3/30 take precedence
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H03G 3/3047 for intermittent signals, e.g. burst signals

Abstract

Systems and methods are described for detecting and correcting saturation in a power amplification circuit. An exemplary circuit comprises a power amplifier that provides an amplified output signal based upon an input signal and a gain control signal; a power detector that provides a detector signal indicative of the amplified signal magnitude; an error amplifier that generates the gain control signal based upon a setpoint signal and the detector signal; and a saturation detector that provides a saturation detection signal indicating whether gain control signal exceeds a reference signal. In another embodiment the circuit comprises an offset generator that provides a correction to the setpoint signal in response to the saturation detection signal indicating that the gain control signal exceeds the reference signal. In still another embodiment the circuit includes an offset cutoff circuit that freezes the correction to the setpoint signal in response to the correction exceeding a threshold.

Claims

1. A power amplification circuit comprising:

a power amplifier having an input to receive an input signal, a power input to receive a power input signal, and an output to provide an amplified output signal based upon the input signal and the power input signal;

an error amplifier having a first input to receive an amplification control signal, a second input, and an output electrically coupled to a power supply node that is adapted to be coupled to a power source, the error amplifier being adapted to control a current provided to the power input of the power amplifier; and

a saturation detector, electrically coupled to the power supply node and to the power input of the power amplifier, to generate a saturation detection signal when the power supply node differs in voltage from the power input by less than a limit voltage.

2. The power amplification circuit of claim 1, wherein the output of the error amplifier is electrically coupled to the power input and to the power supply node through a transistor, and wherein the limit voltage corresponds to a limit voltage of the transistor.

4. The power amplification circuit of claim 1, wherein the power amplifier is not saturated when the power supply node differs in voltage from the power input by more than the limit voltage.

5. The power amplification circuit of claim 1, further comprising:

a power detector to provide a power detector signal indicative of a magnitude of the amplified output signal of the power amplifier;

wherein the second input of the error amplifier is adapted to receive a signal based upon the power detector signal; and

wherein the power detector signal is one of proportional to the logarithm of an RF voltage at the output of the power amplifier and linearly proportional to an RF voltage at the output of the power amplifier.

7. The power amplification circuit of claim 5, further comprising a linear amplifier to receive the power detector signal and to provide an amplified detector signal to the second input of the error amplifier.

8. The power amplification circuit of claim 7, wherein the linear amplifier has unity gain.

10. The power amplification circuit of claim 1, wherein the saturation detector is a comparator.

11. The power amplification circuit of claim 1, further comprising:

a power detector to provide a power detector signal indicative of a magnitude of the amplified output signal of the power amplifier; and

an offset generator circuit to receive the saturation detection signal from the saturation detector and to provide, in response to the saturation detection signal, an offset signal to the first input of the error amplifier;

wherein the second input of the error amplifier is adapted to receive a signal based upon the power detector signal.

12. The power amplification circuit of claim 11, wherein the offset generator circuit comprises:

a current source;

a switch to activate the current source in response to the saturation detection signal; and

a linear amplifier having an input coupled to the current source and an output providing an offset signal, the output electrically coupled to the first input of the error amplifier.

13. The power amplification circuit of claim 12, wherein the output of the linear amplifier is electrically coupled to the first input of the error amplifier through a transistor.

14. The power amplification circuit of claim 12, wherein the offset generator circuit generates a ramping offset signal in response to the saturation detection signal.

15. The power amplification circuit of claim 14, further comprising:

an offset cutoff circuit to freeze the ramping of the offset signal in response to a signal based upon the offset signal exceeding an offset cutoff threshold signal.

17. The power amplification circuit of claim 15, wherein the offset cutoff circuit comprises:

a cutoff comparator having a first input to receive a signal based upon the offset signal, a second input to receive the offset cutoff threshold signal, and an output indicating whether the signal at the first input exceeds the offset cutoff threshold signal, the output being electrically coupled to the offset generator circuit;

wherein the offset generator circuit is deactivated in response to the comparator output indicating that the signal at the first input exceeds the offset cutoff threshold signal.

18. The power amplification circuit of claim 17, further comprising a capacitor electrically coupled between the current source and ground.

3. (canceled)

6. (canceled)

9. (canceled)

16. (canceled)

19. A method of amplifying a first signal using a power amplifier, the method comprising acts of:

receiving a setpoint signal;

generating a current from a power source based upon the setpoint signal;

supplying the current to a power input of the power amplifier;

amplifying, in the power amplifier, the first signal based upon the current; and

providing a saturation detection signal when the power source differs in voltage from the power input by less than a limit voltage.

20. The method of claim 19, wherein the act of generating the current further comprises acts of:

receiving a power detector signal indicative of the amplified first signal; and

generating the current based upon the power detector signal and the gain setpoint signal.

21. The method of claim 19, further comprising acts of:

generating a correction signal in response to the saturation detection signal; and

applying the correction signal to the setpoint signal.

22. The method of claim 21, further comprising acts of:

detecting whether the correction signal exceeds a predetermined cutoff threshold; and

generating a correction cutoff signal in response to the correction signal exceeding the predetermined cutoff threshold.

23. The method of claim 22, further comprising an act of:

ceasing an increase of the correction signal in response to the correction cutoff signal.

24. The method of claim 22, further comprising an act of:

maintaining the correction signal at a constant value in response to the correction cutoff signal.

25-29. -29. (canceled)