VIDEO PROCESSING SYSTEM

• US 20110032422A1
• Filed: 10/18/2010
• Published: 02/10/2011
• Est. Priority Date: 06/05/2008
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: YAMAMOTO, Nariaki, KAIDA, Kunihiro, ISHIDA, Kazuyuki, TANIUCHI, Hiroshi, KINOSHITA, Shun
• Application Number:
  US12/906,705
• Publication Number:
  US 20110032422A1
• Time in Patent Office: Days
• US Class Current: 348/500
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 3/4053 based on super-resolution, i.e. the output image resolution being higher than the sensor resolution

Abstract

In a video processing system which divides HD-size image data into a plurality pieces of sub-image data and performs image processing for upconversion to 4K×2K image data, four image processors synchronous with an HD signal each process a corresponding one of the four pieces of sub-image data. In this case, the image processors process the four pieces of sub-image regions while causing the four pieces of sub-image regions to overlap at their division boundaries, and particularly process the overlapping regions during respective blanking periods. After the image processing of the image processors, the overlapping data is removed. Thereafter, the pieces of image data of the four sub-regions are combined. Therefore, the division boundaries of the pieces of sub-images can be processed without a degradation in image quality.

Claims

1. A video processing system comprising:

N (N is an integer of two or more) image processors each configured to be capable of processing high definition (HD)-size video and be synchronous with an HD synchronization signal;

a region division calculator configured to control data transfer regions of the N image processors; and

an image processing mode controller configured to control image processing modes of the N image processors,

wherein

the N image processors process N respective pieces of sub-video data obtained by dividing video data, and the processed N pieces of sub-video data are combined in a succeeding stage from the N image processors.

2. The video processing system of claim 1, wherein

each of the N image processors includes

an overlapping region calculator configured to calculate an overlapping region at an image boundary between adjacent regions of the N pieces of sub-video data obtained by the region division calculator,

an active period generator configured to generate an active period of video data based on the result of the calculation of the overlapping region calculator,

a data request generator configured to request data transfer corresponding to the active period,

a resizing processor configured to resize boundary video data,

an image quality improving image quality adjuster configured so that a mode thereof is set by the image processing mode controller, and

an image trimmer configured to remove data of the overlapping region.

3. The video processing system of claim 2, wherein

the N image processors perform image processing with respect to the overlapping region during a blanking period of the HD synchronization signal.

4. The video processing system of claim 3, wherein

the image quality improving image quality adjuster has a mechanism configured to store a cumulative value of feature amounts or motion detection results of video, and

cumulative values of the sub-images are integrated and judged by the image processing mode controller, and the result of the judgment is used to set the mode of the image quality improving image quality adjuster again.

5. The video processing system of claim 3, wherein

each of the N image processors includes a combiner configured to combine a plurality of image planes, and

the region division calculator calculates division coordinates and size information of combination screens from screen combination coordinates, and sets the result of the calculation into the data request generators of the N image processors so that screen combination is performed with respect to the N pieces of sub-video data.

6. A video processing system comprising:

N (N is an integer of two or more) image processors each configured to be capable of processing high definition (HD)-size video and be synchronous with an HD synchronization signal; and

an image processing mode controller configured to control image processing modes of the N image processors,

wherein

the N image processors process the same video data, the image processing mode controller sets different image processing modes into the N image processors, and N screens are combined after image processing of the N image processors.

7. A video processing system comprising:

N (N is an integer of two or more) image processors each configured to be capable of processing high definition (HD)-size video and be synchronous with an HD synchronization signal,

wherein

operating clocks of the N image processors can be separately stopped.