INTERFEROMETER FOR DETERMINING OVERLAY ERRORS

• US 20110032535A1
• Filed: 08/04/2009
• Published: 02/10/2011
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Zygo Corporation (Ametek Incorporated)
• Original Assignee: Zygo Corporation (Ametek Incorporated)
• Inventors: Colonna de Lega, Xavier, de Groot, Peter, Liesener, Jan
• Granted Patent: US 8,189,202 B2
• Time in Patent Office: Days
• US Class Current: 356/511
• CPC Class Codes: G01B 2290/70 Using polarization in the interferometer
• CPC Class Codes: G01B 9/02043 Imaging of the Fourier or pupil or back focal plane, i.e. angle resolved imaging
• CPC Class Codes: G01B 9/02057 by using common path configuration, i.e. reference and object path almost entirely overlapping
• CPC Class Codes: G01B 9/02083 characterised by particular signal processing and presentation
• CPC Class Codes: G01B 9/0209 Low-coherence interferometers
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Systems are disclosed that include an interferometer configured to direct test light to an overlay test pad and subsequently combine it with reference light, the test and reference light being derived from a common source, one or more optics configured to direct at least a portion of the combined light to a multi-element detector so that different regions of the detector correspond to different illumination angles of the overlay test pad by the test light, the detector being configured to produce an interference signal based on the combined light, and an electronic processor in communication with the multi-element detector. The overlay test pad comprises a first patterned structure and a second patterned structure and the electronic processor is configured to determine information about the relative alignment between the first and second patterned structures based on the interference signal.

Claims

1. A system comprising:

an interferometer configured to direct test light to an overlay test pad and subsequently combine it with reference light, the test and reference light being derived from a common source;

one or more optics configured to direct at least a portion of the combined light to a multi-element detector so that different regions of the detector correspond to different illumination angles of the overlay test pad by the test light, the detector being configured to produce an interference signal based on the combined light; and

an electronic processor in communication with the multi-element detector,

wherein the overlay test pad comprises a first patterned structure and a second patterned structure and the electronic processor is configured to determine information about the relative alignment between the first and second patterned structures based on the interference signal.

2. The system of claim 1, wherein the information about the relative alignment comprises an overlay error between the first patterned structure and the second patterned structure along a first direction.

3. The system of claim 2, wherein the system is configured to derive a value of a signal from the interference signal, where the signal has a non-zero derivative with respect to the overlay error for a range of displacements of the first patterned structure relative to the second patterned structure along the first direction including a displacement corresponding to a zero overlay error.

4. The system of claim 2, wherein the overlay error is a displacement of the first patterned structure from the second patterned structure along the first direction relative to a nominal position.

5. The system of claim 4, wherein the nominal position corresponds to a non-zero offset between the first and second patterned structures in the first direction.

6. The system of claim 4, wherein the nominal position corresponds to a zero-offset between the first and second patterned structures in the first direction.

7. The system of claim 1, wherein the interferometer defines a pupil and the one or more optics are configured to image the pupil onto the multi-element detector.

8. The system of claim 1, further comprising a polarizer positioned in a path of the test light prior to the overlay test pad and an analyzer positioned in the path of the test light after the overlay test pad.

9. The system of claim 8, wherein the transmission axes of the polarizer and analyzer are parallel.

10. The system of claim 8, wherein the transmission axes of the polarizer and analyzer are non-parallel.

11. The system of claim 10, wherein the transmission axes of the polarizer and analyzer are orthogonal.

12. The system of claim 1, further comprising a waveplate positioned in a path of the test light.

13. The system of claim 1, further comprising a translation stage configured to adjust the relative optical path length between the test and reference light when they form the interference pattern.

14. The system of claim 13, further comprising a base for supporting a test object having the overlay test pad, and wherein the translation stage is configured to move at least a portion of the interferometer relative to the base.

15. The system of claim 14, further comprising the common source, wherein the translation stage is configured to vary the optical path length over a range larger than a coherence length for the common source.

16. The system of claim 1, wherein the first patterned structure is a first grating.

17. The system of claim 16, wherein the second patterned structure is a second grating.

18. The system of claim 17, wherein the first and second gratings are in different layers of the overlay test pad.

19. The system of claim 1, wherein the electronic processor determines the information about the relative alignment based on optical modeling of the first and second patterned structures.

20. The system of claim 1, wherein the electronic processor determines the information about the relative alignment based on differences between measurements taken on multiple test pads having known offset differences.

21. The system of claim 1, wherein the electronic processor determines the information about the relative alignment based on a combination of optical modeling and empirical data obtained from the interference signal.

22. The system of claim 1, wherein the information about the relative alignment comprises an overlay error between the first patterned structure and the second patterned structure along a first direction and an overlay error between the first patterned structure and the second patterned structure along a second direction different from the first direction.

23. The system of claim 1, wherein the interferometer comprises a beam splitter configured to separate input light derived from the common source into the test light and the reference light, and a reference surface positioned to reflect the reference light before it is combined with the test light.

24. The system of claim 23, wherein test light is configured to reflect from the overlay test pad, and the beam splitter in the interferometer is positioned to recombine the test and reference light after they reflect from the respective test and reference surfaces.

25. The system of claim 1, wherein the common source is spatially extended

26. The system of claim 1, further comprising the source, wherein the common source is a broadband source spanning more than 50 nm at full width half maximum.

27. The system of claim 1, wherein the interferometer and one or more optics are part of an interference microscope.

28. The system of claim 27, wherein the interference microscope comprises a Mirau objective.

29. The system of claim 27, wherein the interference microscope comprises a Linnik objective.

30. The system of claim 1, wherein the system is part of a lithography tool.

31. The system of claim 30, wherein the electronic processor is configured to account for tool-induced-shift when determining the information.

32. The system of claim 30, wherein the electronic processor is configured to account for wafer-induced-shift when determining the information.

33. A process for making a display panel, comprising:

providing a component of the display panel, the component supporting an overlay test pad;

determining information about the overlay test pad using the system of claim 1; and

forming the display panel using the component based on the information about the overlay test pad.

34. A process for making an integrated circuit, comprising:

providing a substrate comprising one or more integrated circuit structures;

determining information about the one or more integrated circuit structures using the system of claim 1, where the substrate comprises the overlay test pad and the information is information about the overlay test pad; and

forming the integrated circuit using the substrate based on the information.

35. An interferometry method, comprising:

directing test light to an overlay test pad;

subsequently combining the test light with reference light to form an interference pattern on a multi-element detector so that different regions of the detector correspond to different illumination angles of the overlay test pad by the test light, wherein the test and reference light are derived from a common source and the overlay test pad comprises a first patterned structure and a second patterned structure;

monitoring the interference pattern while varying an optical path difference between the test light and the reference light; and

determining information about the relative alignment between the first and second patterned structures based on the interference pattern.

36. The interferometry method of claim 35, wherein the information about the relative alignment comprises an overlay error between the first patterned structure and the second patterned structure along a first direction.

37. The interferometry method of claim 36, wherein determining the information comprises deriving a value of a signal from the interference pattern, where the signal has a non-zero derivative with respect to the overlay error for a range of displacements of the first patterned structure relative to the second patterned structure along the first direction including a displacement corresponding to a zero overlay error.

38. The interferometry method of claim 36, wherein the overlay error is a displacement of the first patterned structure from the second patterned structure along the first direction relative to a nominal position.

39. The interferometry method of claim 38, wherein the nominal position corresponds to a non-zero offset between the first and second patterned structures in the first direction.

40. The interferometry method of claim 38, wherein the nominal position corresponds to a zero-offset between the first and second patterned structures in the first direction.

41. The interferometry method of claim 35, wherein determining the information comprises determining a spatial frequency transform of the interference pattern.

42. The interferometry method of claim 41, wherein the transform is a Fourier transform.

43. The interferometry method of claim 35, wherein the method is performed using an interference microscope.

44. The interferometry method of claim 35, wherein the method is a low coherence interferometry method.

45. A process for making a display panel, comprising:

providing a component of the display panel, the component supporting an overlay test pad;

determining information about the overlay test pad using the method of claim 35; and

forming the display panel using the component based on the information about the overlay test pad.

46. A process for making an integrated circuit, comprising:

providing a substrate comprising one or more integrated circuit structures;

determining information about the one or more integrated circuit structures using the method of claim 35, where the substrate comprises the overlay test pad and the information is information about the overlay test pad; and

forming the integrated circuit using the substrate based on the information.