UNIVERSAL THREE PHASE CONTROLLERS FOR POWER CONVERTERS

• US 20110032735A1
• Filed: 09/14/2010
• Published: 02/10/2011
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Jin, Taotao, Smedley, Keyue
• Granted Patent: US 8,279,647 B2
• Time in Patent Office: Days
• US Class Current: 363/39
• CPC Class Codes: H02J 3/1842 wherein at least one reactive element is actively controlled by a bridge converter, e.g. active filters
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/4233 using a bridge converter comprising active switches
• CPC Class Codes: H02M 7/2173 in a biphase or polyphase circuit arrangement H02M7/2176 takes precedence; voltage multipliers H02M7/25
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters
• CPC Class Codes: H02M 7/53875 with analogue control of three-phase output
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02E 40/20 Active power filtering [APF]
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
• CPC Class Codes: Y10S 323/91 Two of three phases regulated

Abstract

The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power converters. The universal controller is capable of controlling the power converter in any quadrant of the PQ domain. The universal controller can include a region selection unit, an input selection unit, a reference signal source unit and a control core. The control core can be implemented using one-cycle control, average current mode control, current mode control or sliding mode control and the like. The controller can be configured to control different types of power converters by adjusting the reference signal source. Also provided are multiple modulation methods for controlling the power converter.

Claims

1. A signal adjustment unit within a three-phase controller for a three-phase two-level or three-level converter configured to perform the matrix computation of

2. The signal adjustment unit in claim 1 is configured to perform the matrix computation of

3. A control core within a three-phase controller configured to implement a control key equation to produce plurality of drive signals for a two or three-level converter, wherein two vector voltage signals, v_p and v_n, and two current signals, i_p and i_n, are selected for each operating region;

the i_p and i_n signals are input to a signal adjustment unit;

the voltage signals v_p and v_n are input to multipliers, where they are multiplied by V_m to form scalable voltage signals (V_p*V_m and V_n*V_m);

the scalable voltage signals are then input into a second signal adjustment unit;

the outputs of the two signal adjustment units are combined by adders (subtractors);

the signal from the adders (subtractors) are compensated by compensator G_c(s);

the compensated signals are compared with a sawtooth or triangular signal in order to produce leading-edge, trailing edge, or double edge pulse width modulation (PWM) drive signals Q_p and Q_n.

4. The control core in claim 3, wherein two vector voltage signals, v_p and v_n, and two current signals, i_p and i_n, are selected for each operating region;

the voltage signals v_p and v_n are input to multipliers, where they are multiplied by V_m to form scalable voltage signals (V_p*V_m and V_n*V_m);

the scalable voltage signals (V_p*V_m and V_n*V_m) and the two current signals i_p and i_n are combined by adders (subtractors);

the signals from the adders (subtractors) are input to a signal adjustment unit;

the output signals of the signal adjustment unit are compensated by compensator G_c(s);

the compensated signals are compared with a sawtooth or triangular signal in order to produce leading-edge, trailing edge, or double edge pulse width modulation (PWM) drive signals Q_p and Q_n.

5. The control core in claim 3, wherein two vector voltage signals, v_p and v_n, and two current signals, i_p and i_n, are selected for each operating region;

the voltage signals v_p and v_n are input to multipliers to be multiplied by the voltage signal V_m to form scalable voltage signals (V_p*V_m and V_n*V_m);

the scalable voltage signals are then input into a signal adjustment unit, which outputs signals to one of the inputs of comparators;

a clock generates a clock signal, which is preferably used to generate a synchronized sawtooth signal;

the i_p and i_n signals are input to a signal adjustment unit, whose output signals are linearly combined with the sawtooth signal and sent to the other input of the comparators;

the flip-flops are set by the arrival of the clock signal and reset by the change of state of the comparators, resulting output signals Q_p and Q_n.

6. The control core in claim 3, wherein two vector voltage signals, v_p and v_n, and two current signals, i_p and i_n, are selected for each operating region;

the voltage signals v_p and v_n are input to multipliers to be multiplied by the voltage signal V_m to form scalable voltage signals;

The scalable voltage signals are then input into a signal adjustment unit, which outputs signals to one of inputs of a Schmidt triggers;

the i_p and i_n signals are input to another signal adjustment unit and the output signals are sent to the other inputs of the Schmidt triggers;

the Schmidt triggers generate variable frequency output signals Q_p and Q_n.

7. A control core configured to implement a control key equation to produce plurality of drive signals for a three-phase two or three-level converter, where the combination of the selected line current signals and reference signals are inputs to a signal adjustment unit;

the outputs of the signal adjustment unit are sent to two comparators,

a voltage signal V_m is used to multiply a sawtooth or triangular signal to form a scalable sawtooth or triangular signal;

the sawtooth or triangular signal is sent to two comparators to compare with the two signals from the signal adjustment unit, resulting trailing edge, leading edge, or double edge drive signals Q_p and Q_n.

8. The control core in claim 7, where the combination of the selected line current signals and reference signals are inputs to a signal adjustment unit;

a constant value is integrated and then added to itself by an adder (subtractor);

the output from the adder is multiplied by the voltage signal V_m and is compared with the signals from the signal adjustment unit;

two flip-flops are set by the arrival of the clock signal and reset by the change of state of the comparator signals, resulting drive signals Q_p and Q_n;

the integrator is reset any time after the flip-flops are reset and before the end of the next switching cycle.

9. The control core in claim 7, where the combination of the selected line current signals and reference signals are inputs to a signal adjustment unit;

the voltage signal V_m is integrated and then added to itself by an adder (subtractor);

the output signal from the adder (subtractor) is compared to the signals from the signal adjustment unit;

two flip-flops are set by the arrival of the clock signal and reset by the change of state of the comparator signals, resulting drive signals Q_p and Q_n;

the integrator is reset any time after the flip-flops are reset and before the end of the next switching cycle.

10. A control core includes an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase two-level power converter, wherein the control key equation is:

11. A control core includes an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is:

12. A control core includes an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is:

13. A control core includes an analog, digital, FPGA, microprocessor, and/or microcontroller circuitry configured to implement a control key equation to produce leading edge, trailing edge, or double edge PWM modulation signals to control a three-phase three-level power converter, wherein the control key equation is:

14. A three-phase universal controller, comprising;

a reference signal source unit integrated with a one-cycle control (OCC) controller and configured to inject reference signal into the OCC controller, the OCC controller comprising;

a control core configured to generate a plurality of pulse width modulated (PWM) duty-ratio drive signals;

a voltage loop compensator coupled with the control core and configured to take a taking reference voltage Vref and DC voltage feedback signal proportional to an output DC voltage Vo of a three-phase power converter and provide an output Vm coupled to the control core;

a region selection unit configured to detect a first, second and third time-varying line voltage signals, each line voltage signal having a different phase, and configured to determine a region of operation based on zero crossings of all three time-varying voltage signals;

a signal selection unit coupled with the region selection unit and the control core and configured to select two or more line current signals flowing through the first, second and third time varying line voltage sources and the reference signal and based on the region of operation and provide the selected signals to the control core; and

a drive signal distribution unit coupled to the control core and the region selection unit, the drive signal distribution unit configured to distribute the PWM duty ratio drive signals from the control core to switches of a three-phase converter to realize non grid-tied inverters, static voltage-ampere-reactive (VAR) compensators (SVC), or power converters with the capability of any combination of a power factor corrected rectifier, a grid-tied inverter, a non-grid-tied inverter, a SVC, and an active power filter.

15. The controller of claim 14, wherein the signal selection unit is configured to combine the reference signal with the line current signals flowing through the time varying line voltage sources

16. The controller of claim 14, wherein the reference signals are determinable as a function of an adjustable phase offset value, an adjustable gain value, and the input time varying line voltages to a power converter, wherein

17. The controller of claim 16, wherein the phase offset value and the gain value are predetermined to enable a three-phase two or three-level power converter to operate under zero DC or AC load condition.

18. The controller of claim 14, wherein the control core includes an analog, digital, and/or microcontroller circuitry configured to implement a control key equation to control a three-phase two-level power converter, wherein:

19. The controller of claim 14, wherein the control core includes an analog, digital, and/or microcontroller circuitry configured to implement a control key equation to control a three-phase three-level power converter, wherein:

20. The controller of claim 14, wherein the control core includes an analog, digital, and/or microcontroller circuitry configured to implement a control key equation to control a three-phase three-level power converter, wherein:

21. The controller of claim 14, wherein the control core includes an analog, digital, and/or microcontroller circuitry configured to implement a control key equation to control a three-phase three-level power converter, wherein:

22. The controller of claim 14, wherein the control core is a current mode control core, sliding mode control core, or average current mode control core to control the three-phase two or three level power converter realizing a power factor corrected rectifier, a grid-tied inverter, a non-grid-tied inverter, a SVC, an active power filter, or a converter with the capability of any combination of a power factor corrected rectifier, a grid-tied inverter, a non-grid-tied inverter, a SVC, an active power filter.

23. The controller of claim 14, wherein the line current signals are sensed physically at the line voltage sources or mathematically constituted from signals sensed any where in the power converter.

24. An active power filter comprising

a power converter, and

a controller coupled to the power converter and configured to control the power converter to perform an active power filter function, wherein the controller having a switching frequency that is variable as a function of the rms value of line currents flowing through time-varying line voltage sources to the power converter, wherein the switching frequency is higher at light load conditions and lower at heavy load conditions.

25. A Static VAR compensator comprising

a power converter, and

a controller coupled to the power converter and configured to control the power converter to perform a VAR compensation function, wherein the controller having a switching frequency that is variable as a function of the rms value of line currents flowing through time-varying line voltage sources to the power converter, wherein the switching frequency is higher at light load conditions and lower at heavy load conditions.