NONVOLATILE MEMORY DEVICE OUTPUTTING ANALOG SIGNAL AND MEMORY SYSTEM HAVING THE SAME

• US 20110032758A1
• Filed: 06/23/2010
• Published: 02/10/2011
• Est. Priority Date: 08/07/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Hong Rak, Kong, Junjin, Kim, Jaehong
• Granted Patent: US 8,351,256 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits

Abstract

A memory system and a nonvolatile memory device therein are disclosed. The memory system comprises a memory device outputting a plurality of analog signals during a read operation, a converter to convert the plurality of analog signals into binary data, and a memory controller to operate an error correction operation on the binary data. The error correction operation uses a soft decision algorithm.

Claims

1. A memory system comprising:

a memory device including a plurality of memory cells, the memory device being configured to output a plurality of analog signals from selected memory cells of the plurality of memory cells during a read operation;

a converter configured to convert the plurality of analog signal into binary data; and

a memory controller configured to perform an error correction operation on the binary data.

2. The memory system of claim 1, wherein the memory controller is configured to supply an analog read command to the memory device, and the read operation is performed based on the analog read command.

3. The memory system of claim 1, wherein the plurality of analog signals each have a voltage level and each voltage level of the plurality of analog signals is based on a threshold voltage of each of the selected memory cells.

4. The memory system of claim 1, wherein the converter is configured to receive a reference signal and convert the plurality of analog signals into the binary data based on the reference signal, a resolution of the binary data being determined by the reference signal.

5. The memory system of claim 1, wherein the converter is included in at least one of the memory device and the memory controller.

6. The memory system of claim 1, wherein the error correction operation is a soft decision operation performed using the binary data.

7. The memory system of claim 1, wherein the memory device further includes

a memory cell array including the plurality of memory cells, the plurality of memory cells being nonvolatile memory cells;

a page buffer configured to sense and latch data of the plurality of nonvolatile memory cells through a plurality of bit lines;

an analog output circuit configured to output the plurality of analog signals that are detected from the plurality of bit lines during the read operation;

a switch configured to selectively connect the plurality of bit lines to the page buffer or the analog output circuit; and

a control logic configured to control the switch to output the plurality of analog signals, in response to a command from the memory controller.

8. The memory system of claim 7, wherein the analog output circuit includes an analog amplifier configured to amplify the plurality of analog signals and an analog output buffer configured to output the amplified plurality of analog signals.

9. The memory system of claim 7, wherein the analog output circuit is further configured to output the plurality of analog signals without discrete processing.

10. A nonvolatile memory device, comprising:

a memory cell array including a plurality of memory cells;

an analog output circuit configured to output a plurality of analog signals detected on bit lines coupled to selected memory cells from among the plurality of memory cells during a read operation;

a voltage generator configured to generate an analog read voltage for the read operation; and

a control logic configured to control the voltage generator to supply the analog read voltage to the selected memory cells, and configured to control the analog output circuit to output the plurality of analog signals externally.

11. The nonvolatile memory device of claim 10, wherein the nonvolatile memory device further includes a converter configured to convert the plurality of analog signals to binary data.

12. The nonvolatile memory device of claim 11, wherein the analog output circuit is configured to output the plurality of analog signals to the converter, and the converter is configured to convert the plurality of analog signals to binary data and output the binary data externally.

13. The memory system of claim 12, wherein the analog output circuit is further configured to output the plurality of analog signals without discrete processing.

14. A nonvolatile memory device, comprising:

a memory cell array including a plurality of memory cells;

a voltage generator configured to generate an analog read voltage;

an analog output circuit configured to output a plurality of analog signals detected on bit lines coupled to selected memory cells from among the plurality of memory cells during a read operation, each of the plurality of analog signals being based on the analog read voltage and a threshold voltage of each corresponding memory cell of the selected memory cells; and

a converter configured to convert the plurality of analog signals to binary data by performing a comparison based on each of the plurality of analog signals and the analog read voltage.

15. The nonvolatile memory device of claim 14, wherein the converter is configured to convert the plurality of analog signals to binary data based on a difference between each of the plurality of analog signals and the analog read voltage.

16. The nonvolatile memory device of claim 14, further comprising:

a control logic configured to control the voltage generator to supply the analog read voltage to the selected memory cells, and configured to control the analog output circuit to output the plurality of analog signals externally.

17. The nonvolatile memory device of claim 14, wherein the analog output circuit is further configured to output the plurality of analog signals without discrete processing.