EDGE CONNECT WAFER LEVEL STACKING
First Claim
1. A method of making a stacked microelectronic package, the method comprising the steps of:
- forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto the adhesive layer of a substrate, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and
thenforming initial notches in said first subassembly so as to expose said traces and coating an adhesive layer on said first subassembly so as to fill said initial notches with adhesive and cover said traces; and
thenstacking a second subassembly including a plurality of microelectronic elements onto said adhesive layer of said first subassembly, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and
thenforming initial notches in said second subassembly so as to expose said traces and coating an adhesive layer on said second subassembly so as to fill said initial notches with adhesive and cover said traces; and
thenforming notches in the adhesive layers so as to expose the traces of at least some of the plurality of microelectronic elements; and
forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.
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Accused Products
Abstract
A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.
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Citations
7 Claims
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1. A method of making a stacked microelectronic package, the method comprising the steps of:
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forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto the adhesive layer of a substrate, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and
thenforming initial notches in said first subassembly so as to expose said traces and coating an adhesive layer on said first subassembly so as to fill said initial notches with adhesive and cover said traces; and
thenstacking a second subassembly including a plurality of microelectronic elements onto said adhesive layer of said first subassembly, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and
thenforming initial notches in said second subassembly so as to expose said traces and coating an adhesive layer on said second subassembly so as to fill said initial notches with adhesive and cover said traces; and
thenforming notches in the adhesive layers so as to expose the traces of at least some of the plurality of microelectronic elements; and
forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification