EDGE CONNECT WAFER LEVEL STACKING

• US 20110033979A1
• Filed: 10/20/2010
• Published: 02/10/2011
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Oganesian, Vage, Haba, Belgacem
• Granted Patent: US 8,431,435 B2
• Time in Patent Office: Days
• US Class Current: 438/109
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.

Claims

1. A method of making a stacked microelectronic package, the method comprising the steps of:

forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto the adhesive layer of a substrate, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and

then

forming initial notches in said first subassembly so as to expose said traces and coating an adhesive layer on said first subassembly so as to fill said initial notches with adhesive and cover said traces; and

then

stacking a second subassembly including a plurality of microelectronic elements onto said adhesive layer of said first subassembly, at least some of the plurality of microelectronic elements of said first subassembly having traces that extend to respective edges of the microelectronic elements; and

then

forming initial notches in said second subassembly so as to expose said traces and coating an adhesive layer on said second subassembly so as to fill said initial notches with adhesive and cover said traces; and

then

forming notches in the adhesive layers so as to expose the traces of at least some of the plurality of microelectronic elements; and

forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.

2. The method of claim 1, wherein a relief channel, aligned with the saw lanes of the substrate, is formed partially through the substrate prior to stacking said first subassembly onto the adhesive layer of a substrate.

3. The method of claim 1, wherein the substrate, the first subassembly and the second subassembly include saw lanes, wherein after stacking the microelectronic assembly, the saw lanes of the substrate, the first subassembly and the second subassembly are aligned and, after coating the adhesive layer on the second subassembly, the notches are formed at the saw lanes of the respective subassemblies.

4. The method of claim 3, further comprising the step of dicing through the saw lanes of the substrate to form individual stacked packages.

5. The method of claim 1, wherein the step of forming notches does not include forming notches in the substrate.

6. The method of claim 3, wherein the step of forming notches does not include forming notches in the substrate.

7. The method of claim 1, wherein at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend across said saw lanes of said first subassembly and said second subassembly.