METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING POROUS LOW DIELECTRIC CONSTANT LAYER FORMED FOR INSULATION BETWEEN METAL LINES

• US 20110034028A1
• Filed: 10/18/2010
• Published: 02/10/2011
• Est. Priority Date: 06/21/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: PARK, Chang Soo
• Granted Patent: US 8,273,667 B2
• Time in Patent Office: Days
• US Class Current: 438/674
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric

Abstract

The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers.

Claims

1. A method for manufacturing a semiconductor device, comprising the step of:

forming a porous low dielectric constant layer for insulation between metal lines,

wherein the porous low dielectric constant layer comprises an insulation layer including fillers, and the fillers comprise silicon.

2. The method according to claim 1, wherein the fillers are a solid type.

3. The method according to claim 1, wherein the silicon is formed through electrochemical etching of a silicon wafer in an HF solution to have a plurality of pores.

4. The method according to claim 3, wherein a size of the pores in the silicon is controlled through adjustment of a density of a current applied in the electrochemical etching, a composition of an electrolyte, an etching time, and a doping concentration of a silicon substrate.

5. The method according to claim 1, wherein the porous low dielectric constant layer is formed through any one of a spin coating process, an ALD process and a CVD process.

6. The method according to claim 5, wherein forming the porous low dielectric constant layer through the spin coating process comprises the steps of:

mixing fillers in an SOG-based or an organic polymer-based insulation layer;

spin-coating the insulation layer having the fillers mixed therein; and

backing the spin-coated insulation layer having the fillers mixed therein.

7. The method according to claim 5, wherein forming the porous low dielectric constant layer through the ALD process or the CVD process comprises the steps of:

forming fillers; and

depositing an organic or inorganic-based insulation layer on the fillers.

8. The method according to claim 1, wherein the porous low dielectric constant layer is formed to have a double-layered structure.

9. The method according to claim 8, wherein the porous low dielectric constant layer having the double-layered structure is formed such that an upwardly positioned layer has a lower dielectric constant than a downwardly positioned layer.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming a porous low dielectric constant layer including fillers made of silicon on a semiconductor substrate which is formed with a lower metal line;

etching the porous low dielectric constant layer so as to expose the lower metal line and defining a metal line forming region in which an upper metal line is to be formed; and

filling a metal layer in the metal line forming region so as to form an upper metal line which comes into contact with the lower metal line.

11. The method according to claim 10, wherein the fillers are a solid type.

12. The method according to claim 10, wherein the silicon is formed through electrochemical etching of a silicon wafer in an HF solution to have a plurality of pores.

13. The method according to claim 12, wherein a size of the pores in the silicon is controlled through adjustment of a density of a current applied in the electrochemical etching, a composition of an electrolyte, an etching time, and a doping concentration of a silicon substrate.

14. The method according to claim 10, wherein the porous low dielectric constant layer is formed through any one of a spin coating process, an ALD process and a CVD process.

15. The method according to claim 14, wherein forming the porous low dielectric constant layer through the spin coating process comprises the steps of:

mixing fillers in an SOG-based or an organic polymer-based insulation layer;

spin-coating the insulation layer having the fillers mixed therein; and

backing the spin-coated insulation layer having the fillers mixed therein.

16. The method according to claim 14, wherein forming the porous low dielectric constant layer through the ALD process or the CVD process comprises the steps of:

forming fillers; and

depositing an organic or inorganic-based insulation layer on the fillers.

17. The method according to claim 10, wherein the porous low dielectric constant layer is formed to have a double-layered structure.

18. The method according to claim 17, wherein the porous low dielectric constant layer having the double-layered structure is formed such that an upwardly positioned layer has a lower dielectric constant than a downwardly positioned layer.

19. The method according to claim 10, wherein, before the step of a porous low dielectric constant layer including fillers, the method further comprises the step of:

forming an insulation layer not including fillers, on the semiconductor substrate which is formed with the lower metal line.

20. A method for manufacturing a semiconductor device, comprising the step of:

forming a porous low dielectric constant layer having a double-layered structure for insulation between metal lines,

wherein the porous low dielectric constant layer comprises an insulation layer including fillers, and

wherein the porous low dielectric constant layer having the double-layered structure is formed such that an upwardly positioned layer has a lower dielectric constant than a downwardly positioned layer.