Integrated Circuit Implementation and Fault Control System, Device, and Method

• US 20110034964A1
• Filed: 02/27/2009
• Published: 02/10/2011
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Original Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Inventors: Bi, Yafei, Leichner, Robert, Li, Haifeng, Thompson, Todd, Zdeblick, Mark
• Granted Patent: US 8,473,069 B2
• Time in Patent Office: Days
• US Class Current: 607/5
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/05 for implantation or insertion into the body, e.g. heart electrode A61N1/06 takes precedence
• CPC Class Codes: A61N 1/37 Monitoring; Protecting
• CPC Class Codes: A61N 1/378 Electrical supply

Abstract

Apparatus and methods enable robust, reliable control for implantable medical devices, including cardiac pacemakers, defibrillators and cardiac resynchronization devices. Integrated circuits in the devices have minimized interfaces, can derive power from the interface signals, and have high voltage and latch-up protection. A device lead has a power generation circuit and a switching circuit using cascaded PMOS transistors for operating with a stable voltage despite fluctuations in the supplied voltage. The lead has control electronics that provide a very low impedance between an electrode and a lead conductor during most of the duration of a pacing pulse, but during a brief initial portion of the pacing pulse, provide a very high impedance to permit charging up a power supply that is local to the control electronics. A method of stabilizing the external impedance and a system for fault detection and fault recovery for an implantable device are also provided.

Claims

1-131. -131. (canceled)

132. An implantable system, comprising:

(a) a controller configured to provide first and second lead lines, the first and second lead lines being switched in polarity during a first mode; and

(b) a plurality of implantable integrated circuits coupled to the first and second lead lines, wherein each of the implantable integrated circuits is configured to derive a plurality of internal power supplies from the first and second lead lines.

133. The implantable system according to claim 132, wherein the plurality of internal power supplies comprises a substrate connection and an n-well connection for an electrode switch.

134. The implantable system according to claim 132, further comprising protection circuitry for each of the implantable integrated circuits, the protection circuitry being activated when the one of the first and second lead lines is increased in voltage to greater than about 5.5 V.

135. A supply circuit in an implantable satellite integrated circuit, the circuit comprising:

(a) a resistor divider network coupled to a first interface signal via a switch;

(b) a transistor coupled to a first supply, and controllable by a node of the resistor divider network; and

(c) a buffer configured to receive an output from the transistor, and to open the switch when the first interface signal is greater than a first predetermined level.

136. The implantable system according to claim 135, further comprising a second supply coupled to the resistor divider network, and a third supply configured to be a diode drop below the second supply.

137. (canceled)

138. An apparatus comprising:

(a) an in-body computing system;

(b) a plurality of electrodes in electrical contact with a patient'"'"'s body, the plurality of electrodes being selectively configurable for electrical connection with the in-body computing system; and

(c) an external impedance stabilizer, the external impedance stabilizer having a configuration mode in which all of the plurality of electrodes are decoupled from the in-body computing system and an operating mode in which selected electrodes of the plurality of electrodes are coupled to the in-body computing system.

139. The apparatus according to claim 138, further comprising:

a control circuit, the control circuit adapted to, while the external impedance stabilizer is in the configuration mode, configure the plurality of electrodes by selecting which electrodes of the plurality of electrodes will be coupled to the in-body computing system during the operating mode.

140. The apparatus according to claim 139, wherein, while the external impedance stabilizer is in the operating mode, the external impedance stabilizer decouples the control circuit from the in-body computing system.

141. The apparatus according to claim 138, wherein the in-body computing system is

a cardiac pacemaker and the plurality of electrodes are located on a pacemaker lead, and wherein, during the operating mode, the in-body computing system delivers pacing signals to the selected electrodes of the plurality of electrodes.

152. The apparatus according to claim 138, wherein the in-body computing system is an implantable cardiac defibrillator and the plurality of electrodes are located on a cardiac defibrillator lead, and wherein, during the operating mode, the in-body computing system delivers cardiac resynchronization or defibrillation signals to the selected electrodes of the plurality of electrodes.

142. A fault recovery system for an implantable device having a multiplicity of components, the fault recovery system comprising:

a logic unit adapted to correct a fault in one or more components of the implantable device by selectively applying at least one fault correction strategy, wherein the fault correction strategies are selected from;

signal re-programming for at least one failed component, virtual component replacement through component re-selection, weighted selection of component replacement based on weighted failure probability and faultiness level, signal normalization for deteriorating sensor components, and circuit fault re-routing and isolation.

143. The fault recovery system according to claim 142, wherein the multiplicity of components are arranged on a plurality of satellites, and wherein, during fault correction, the logic unit is adapted to apply at least one of the fault correction strategies to components on at least one of the satellites.

144. The fault recovery system according to claim 142, wherein the logic unit is adapted to iteratively apply the fault correction strategies until satisfactory operation of the implantable device is achieved or until the logic unit determines that satisfactory operation of the implantable device cannot be achieved.

145. The fault recovery system of claim 142, wherein the implantable

device is a cardiac pacemaker and the multiplicity of components comprise a multiplicity of electrodes located on a pacemaker lead, and wherein, during fault correction, the logic unit is adapted to re-select which of the multiplicity of electrodes are to be connected to the cardiac pacemaker.

153. The fault recovery system of claim 142, wherein the implantable device is an implantable cardiac defibrillator and the multiplicity of components comprise a multiplicity of electrodes located on a cardiac defibrillator lead, and wherein, during fault correction, the logic unit is adapted to re-select which of the multiplicity of electrodes are to be connected to the implantable cardiac defibrillator.

146. A lead for use with a pacing voltage source, the pacing voltage source comprising first and second terminals, the lead comprising:

a satellite, the satellite comprising control electronics and an electrode, the control electronics having first and second terminals,

the lead comprising a conductor along its length, the conductor comprising a first end and a second end, the first end of the conductor disposed for electrical contact with the pacing voltage source, the second end of the conductor connecting with the first terminal of the control electronics, the second terminal of the control electronics in electrical contact with the electrode;

the control electronics responsive to a pulse from the pacing voltage source for maintaining a first impedance between the first and second terminals of the control electronics for an interval between one and fifty microseconds;

the control electronics comprising a power extraction component disposed, while the first impedance is maintained, to accumulate a power supply within the control electronics;

the control electronics further responsive to the passage of the interval for maintaining a second impedance between the first and second terminals of the control electronics, the second impedance being at least as small as one-tenth of the first impedance.

147-151. -151. (canceled)