Software-Defined Radio Using Multi-Core Processor

• US 20110035522A1
• Filed: 08/04/2009
• Published: 02/10/2011
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Tan, Kun, Zhang, Yongguang, Zhang, Jiansong
• Granted Patent: US 8,565,811 B2
• Time in Patent Office: Days
• US Class Current: 710/107
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A radio control board passes a plurality of digital samples between a memory of a computing device and a radio frequency (RF) transceiver coupled to a system bus of the computing device. Processing of the digital samples is carried out one or more cores of a multi-core processor to implement a software-defined radio.

Claims

1. A radio control board, comprising:

a radio frequency (RF) controller for communicating with an RF front end coupled to the radio control board;

a bus controller for coupling the radio control board for communication with a system bus of the computing device;

a direct memory access DMA controller for receiving digital samples of received radio waveforms from the RF front end via the RF controller and for storing the received digital samples in a memory on a computing device via the system bus, wherein the bus controller passes the received digital samples from the DMA controller to the system bus for storage in the memory on the computing device;

wherein the bus controller is configured to receive generated digital samples from the computing device via the system bus for delivery to the RF controller;

wherein the RF controller is configured to receive the generated digital samples from the bus controller and pass the generated digital samples to the RF front end for transmission as radio waveforms.

2. The radio control board according to claim 1, wherein the bus is a Peripheral Component Interconnect Express (PCIe) bus.

3. The radio control board according to claim 1, further comprising an onboard memory on the radio control board for storing the generated digital samples temporarily prior to passing the generated digital samples to the RF front end and/or for storing the received digital samples temporarily prior to passing the received digital samples to the memory on the computing device.

4. The radio control board according to claim 1, further comprising an onboard memory on the radio control board for storing an pre-generated ACK waveform, wherein during demodulation of a received frame, the pre-generated ACK is prepared for sending in response to the frame for providing an acknowledgement of receiving the received frame, wherein, following a check of the received frame, the pre-generated ACK is delivered to the RF front end for transmission to acknowledge receipt of the received frame.

5. The radio control board according to claim 1,

wherein the memory on the computing device is organized into a plurality of slots,

wherein each slot begins with a descriptor that contains an indicator that indicates whether the data in the slot has been processed,

wherein the radio control board sets the indicator when a slot of data is written,

wherein a processor on the computing device determines from the indicator whether to process the data in the slot or flush the data corresponding to the slot.

6. The radio control board according to claim 1, further comprising:

a first FIFO buffer on the radio control board located between the RF front end and the DMA controller for temporarily storing the digital samples received from the RF front end prior to the DMA controller storing the digital samples on the memory of the computing device;

a second FIFO buffer on the radio control board between the bus controller and the RF front end for temporarily storing processed digital samples received from the computing device prior to delivery of the generated digital samples to the RF front end.

7. A method implemented on a computing device, the method comprising:

receiving a plurality of digital samples in a memory of the computing device from a radio frequency (RF) receiver coupled to a system bus of the computing device;

performing physical layer processing and/or media access control (MAC) layer processing of the digital samples using one or more first cores of a multi-core processor.

8. The method according to claim 7, wherein the one or more first cores are dedicated to processing the digital samples while one or more second cores of the multi-core processor execute one or more applications.

9. The method according to claim 8, wherein the one or more first cores are dedicated to processing of the digital samples by initiating a kernel thread for processing the digital samples, and raising the priority of the thread and/or an interrupt request level of the kernel thread so that the kernel thread runs exclusively on a particular first core until termination.

10. The method according to claim 9, further comprising removing interrupt handlers for installed devices from the particular first core to prevent the particular first core from being interrupted by hardware until termination of the kernel thread.

11. The method according to claim 7, further comprising:

passing the plurality of digital samples from the RF receiver to the memory of the computing device by a radio control board coupled between the RF receiver and the memory of the computing device,

wherein the digital samples are passed from the RF receiver to the memory of the computing device on a Peripheral Component Interconnect Express (PCIe) bus.

12. The method according to claim 7, further comprising using single instruction multiple data (SIMD) instructions to simultaneously process an array of the digital samples during the physical layer processing and or MAC layer processing of the plurality of digital samples.

13. The method according to claim 7, further comprising:

pre-calculating one or more lookup tables for one or more physical layer algorithms and/or one or MAC layer algorithms;

storing the one or more lookup tables in a cache associated with the one or more first cores;

accessing the lookup tables during processing of the digital samples in place of performing calculations for the corresponding algorithms during physical layer processing and/or MAC layer processing of the digital samples.

14. The method according to claim 7, further comprising performing physical layer processing of the digital samples using at least two first cores of the multi-core processor, wherein a first sub-pipeline of functional physical layer blocks is executed on a first one of the first cores and a second sub-pipeline of physical layer blocks is executed on a second one of the first cores.

15. The method according to claim 14, wherein one of the first cores acts as a consumer of data and the other first core acts as a producer of data, further comprising:

providing a circular First In First Out (FIFO) buffer between the consumer and the producer, wherein the FIFO buffer includes a plurality of data slots, wherein each data slot includes an indicator as to whether the data slot is full or empty, wherein the FIFO buffer further includes a pointer for the consumer and a pointer for the producer;

wherein the consumer pointer follows the producer pointer to take data from the FIFO for consumption by the consumer.

16. The method according to claim 7,

wherein MAC layer processing is implemented as a first kernel thread running on a first one of the first cores, and wherein at least a portion of the physical layer processing is implemented as a second kernel thread running on a second one of the first cores, the method further comprising:

raising the priority and/or an interrupt request level of each of the first kernel thread and the second kernel thread so that each kernel thread runs exclusively on the corresponding one of the first cores until termination of the respective kernel thread.

17. Computer-readable storage media containing processor-executable instructions adapted to be executed by a processor for implementing one or more modules comprising:

a management module for controlling a radio control board for delivery of digital samples between a radio frequency (RF) transceiver and a memory on a computing device via a system bus;

a physical layer module for processing the digital samples on one or more cores of a multi-core processor.

18. The computer-readable storage media according to claim 17,

wherein the management module further includes a direct memory access (DMA) manager for controlling a DMA controller on the radio control board,

wherein the DMA controller delivers the digital samples from the RF transceiver to a DMA memory portion of the memory on the computing device,

wherein the DMA manager sets a flag on the digital samples when written to the memory,

wherein the processor processing the digital samples checks the flag before reading data in a cache to avoid inconsistency between the data in the cache and the data in the DMA memory.

19. The system according to claim 17, wherein the management module includes a Peripheral Component Interconnect Express (PCIe) driver for controlling the radio control board for delivery of the digital samples between the radio frequency (RF) transceiver and the memory on the computing device via the system bus, wherein the system bus is a PCIe bus.

20. The system according to claim 17, further including a media access control module, wherein the media access control module and the physical layer module are controlled by the management module for processing digital samples on a multi-core processor.