MICROPROCESSOR HAVING A LOW-POWER MODE AND A NON-LOW POWER MODE, DATA PROCESSING SYSTEM AND COMPUTER PROGRAM PRODUCT

• US 20110035613A1
• Filed: 04/11/2008
• Published: 02/10/2011
• Est. Priority Date: 04/11/2008
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rancurel, Vianney, Meunier, Gregory, Bufferne, Vincent
• Granted Patent: US 8,756,446 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock signal, which in the non-low power mode has a first frequency and in the low power mode has a second frequency lower than the first frequency. A hardware timer is present, for scheduling an execution of an event by the microprocessor at a future point in time. The hardware timer is connected to the clock for determining a period of time between a current point in time and a point in time the event based on a number of clock cycles of the clock signal. A timer controller can determine, when the data processing system switches from the low power mode to the non-low power mode, a number of clock cycles of a clock signal with the first frequency that corresponds to a low-power mode period during which the microprocessor has been in the low power mode and adjusting the hardware timer based on the determined number.

Claims

1. A microprocessor having a low-power mode and a non-low power mode, said microprocessor comprising:

a processor core for executing instructions provided to said microprocessor;

a clock providing a clock signal which in said non-low power mode has a first frequency and in said low power mode has a second frequency lower than said first frequency;

a hardware timer for scheduling an execution of an event by said microprocessor at a future point in time, said hardware timer being connected to said clock for determining a period of time between a current point in time and a point in time said event based on a number of clock cycles of said clock signal;

a timer controller for determining, when said data processing system switches from said low power mode to said non-low power mode, a number of clock cycles of a clock signal with said first frequency that corresponds to a low-power mode period during which said microprocessor has been in said low power mode and adjusting said hardware timer based on said determined number.

2. A microprocessor as claimed in claim 1, wherein said hardware timer includes a counter connected to said clock for counting a counted number of clock cycles of said clock signal.

3. A microprocessor as claimed in claim 1, wherein said timer controller includes a converter for adjusting a counter value of said counter and/or an expiry time to which said hardware timer is set based on said number of clock cycles of said clock during said low-power mode period.

4. A data processing system comprising:

a microprocessor as claimed in claim 1;

a memory including data representing instructions executable by said microprocessor, said instructions including timer control instructions for determining, when said microprocessor switches from said low power mode to said non-low power mode, a number of clock cycles of a clock signal with said first frequency that corresponds to a low-power mode period during which said data processing system has been in said low power mode and adjusting said hardware timer based on said determined number.

5. A data processing system as claimed in claim 1, wherein said instructions include a set of instructions representing an operating system, said operating system forming an interface between said microprocessor and applications running on said microprocessor;

said set including said timer control instructions.

7. A microprocessor as claimed in claim 2, wherein said timer controller includes a converter for adjusting a counter value of said counter and/or an expiry time to which said hardware timer is set based on said number of clock cycles of said clock during said low-power mode period.

8. A data processing system comprising:

a microprocessor as claimed in claim 2;

a memory including data representing instructions executable by said microprocessor, said instructions including timer control instructions for determining, when said microprocessor switches from said low power mode to said non-low power mode, a number of clock cycles of a clock signal with said first frequency that corresponds to a low-power mode period during which said data processing system has been in said low power mode and adjusting said hardware timer based on said determined number.

9. A data processing system comprising:

a microprocessor as claimed in claim 3;

a memory including data representing instructions executable by said microprocessor, said instructions including timer control instructions for determining, when said microprocessor switches from said low power mode to said non-low power mode, a number of clock cycles of a clock signal with said first frequency that corresponds to a low-power mode period during which said data processing system has been in said low power mode and adjusting said hardware timer based on said determined number.

10. A data processing system comprising:

a microprocessor as claimed in claim 7;

a memory including data representing instructions executable by said microprocessor, said instructions including timer control instructions for determining, when said microprocessor switches from said low power mode to said non-low power mode, a number of clock cycles of a clock signal with said first frequency that corresponds to a low-power mode period during which said data processing system has been in said low power mode and adjusting said hardware timer based on said determined number.

11. A data processing system as claimed in claim 8, wherein said instructions include a set of instructions representing an operating system, said operating system forming an interface between said microprocessor and applications running on said microprocessor;

said set including said timer control instructions.

12. A data processing system as claimed in claim 9, wherein said instructions include a set of instructions representing an operating system, said operating system forming an interface between said microprocessor and applications running on said microprocessor;

said set including said timer control instructions.

6. (canceled)

13. A data processing system as claimed in claim 17, wherein said instructions include a set of instructions representing an operating system, said operating system forming an interface between said microprocessor and applications running on said microprocessor;

said set including said timer control instructions.