SEMICONDUCTOR STRUTURE AND METHOD OF FORMING THE SAME

• US 20110037113A1
• Filed: 08/17/2009
• Published: 02/17/2011
• Est. Priority Date: 08/17/2009
• Status: Active Grant

• Current Assignee: Excelliance Mos Corporation
• Original Assignee: Excelliance Mos Corporation
• Inventors: Liu, Chu-Kuang
• Granted Patent: US 8,222,678 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/782 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor structure including a substrate, at least one power MOSFET, a floating diode or a body diode, and at least one Schottky diode is provided. The substrate has a first area, a second area and a third area. The second area is between the first area and the third area. The at least one power MOSFET is in the first area. The floating diode or the body diode is in the second area. The at least one Schottky diode is in the third area. Further, the contact plugs of the power MOSFET and the Schottky diode include tungsten and are electronically connected to each other.

Claims

1. A semiconductor structure, comprising:

a substrate of a first conductivity type, having a first area, a second area and a third area, wherein the second area is disposed between the first area and the third area;

an epitaxial layer of the first conductivity type, disposed on the substrate;

a body layer of a second conductivity type, disposed in the epitaxial layer in the first area and the second area;

a first gate and a second gate, disposed in the body layer and in a portion of the epitaxial layer outside the body layer, wherein the first gate is disposed between the first area and the second area, and the second gate is disposed between the second area and the third area;

a first contact plug, disposed in a portion of the body layer in the first area;

a second contact plug, at least disposed in the epitaxial layer in the third area and contacting the epitaxial layer and the second gate, wherein the first contact plug is electrically connected to the second contact plug; and

a first doped region of the first conductivity type, disposed in the body layer between the first contact plug and the first gate.

2. The semiconductor structure as claimed in claim 1, wherein the second contact plug is embedded into the second gate.

3. The semiconductor structure as claimed in claim 1, wherein the second contact plug is disposed in the epitaxial layer in the third area and a portion of the second area, and the second gate is disposed under the second contact plug.

4. The semiconductor structure as claimed in claim 3, wherein the body layer in the second area covers a sidewall and a portion of a bottom of the second contact plug.

5. The semiconductor structure as claimed in claim 1, further comprising a second doped region of the second conductivity type disposed around a bottom and a portion of a sidewall of the first contact plug.

6. The semiconductor structure as claimed in claim 1, further comprising:

a dielectric layer, disposed on the substrate and exposing the first contact plug and the second contact plug; and

a metal layer, disposed on the substrate and covering the dielectric layer, the first contact plug and the second contact plug.

7. The semiconductor structure as claimed in claim 6, wherein a material of the metal layer comprises AlSiCu.

8. The semiconductor structure as claimed in claim 1, wherein the first contact plug and the second contact plug each comprise a first metal layer and a barrier layer around the first metal layer.

9. The semiconductor structure as claimed in claim 8, wherein a material of the first metal layer comprises tungsten.

10. The semiconductor structure as claimed in claim 1, wherein the first conductivity type is N-type while the second conductivity type is P-type;

or the first conductivity type is P-type while the second conductivity type is N-type.

11. The semiconductor structure as claimed in claim 1, wherein a cell pitch of the semiconductor structure is smaller than or equal to about 1.5 μ

m.

12. The semiconductor structure as claimed in claim 1, wherein a cell density of the semiconductor structure is greater than or equal to about 300 M cell/inch².

13. The semiconductor structure as claimed in claim 1, wherein the second gate is a floating gate.

14. The semiconductor structure as claimed in claim 1, wherein the first area surrounds the second area and the second area surrounds the third area.

15. The semiconductor structure as claimed in claim 1, further comprising at least one third gate disposed in the epitaxial layer in the third area and located under the second contact plug.

16. The semiconductor structure as claimed in claim 15, wherein the third gate is a floating gate.

17. A semiconductor structure, comprising:

a substrate having a first area, a second area and a third area, wherein the second area is disposed between the first area and the third area;

at least one power metal-oxide-semiconductor field effect transistor (power MOSFET), disposed in the first area;

a floating diode or a body diode, disposed in the second area; and

at least one Schottky diode, disposed in the third area,

wherein contact plugs of the power MOSFET and the Schottky diode comprise tungsten and are electrically connected to each other.

18. The semiconductor structure as claimed in claim 17, wherein the first area surrounds the second area and the second area surrounds the third area.

19. The semiconductor structure as claimed in claim 17, wherein a cell pitch of the semiconductor structure is smaller than or equal to about 1.5 μ

m.

20. The semiconductor structure as claimed in claim 17, wherein a cell density of the semiconductor structure is greater than or equal to about 300 M cell/inch².

21. A method of forming a semiconductor structure, comprising:

providing a substrate of a first conductivity type, the substrate having a first area, a second area, and a third area, wherein the second area is disposed between the first area and the third area;

forming an epitaxial layer of the first conductivity type on the substrate;

forming a first gate and a second gate in the epitaxial layer, wherein the first gate is disposed between the first area and the second area and the second gate is disposed between the second area and the third area;

forming a body layer of a second conductivity type in the epitaxial layer in the first area and the second area;

forming a first doped region of the first conductivity type in the body layer in the first area;

forming a dielectric layer on the substrate to expose a portion of the first doped region in the first area, at least the epitaxial layer in the third area and at least a portion of the second gate;

removing a portion of the first doped region, a portion of the epitaxial layer and a portion of the second gate by using the dielectric layer as a mask, so as to form a first opening in the first doped region and in a portion of the body layer outside the first doped region in the first area, and a second opening in the epitaxial layer in the third area and in a portion of the second gate;

filling a first metal layer in the first opening and the second opening; and

forming a second metal layer on the substrate to cover the dielectric layer and the first metal layer.

22. The method as claimed in claim 21, wherein the dielectric layer exposes a portion of the first doped region in the first area, the epitaxial layer in the third area, the entire second gate and a portion of the body layer in the second area.

23. The method as claimed in claim 21, after the step of forming the first opening and the second opening and before the step of filling the first metal layer, further comprising forming a second doped region of the second conductivity type in a bottom of the first opening.

24. The method as claimed in claim 23, after the step of forming the second doped region and before the step filling the first metal layer, further comprising forming a barrier layer in the first opening and the second opening.

25. The method as claimed in claim 21, wherein a material of the first metal layer comprises tungsten.

26. The method as claimed in claim 21, wherein a material of the second metal layer comprises AlSiCu.

27. The method as claimed in claim 21, wherein the first conductivity type is N-type while the second conductivity type is P-type;

or the first conductivity type is P-type while the second conductivity type is N-type.

28. The method as claimed in claim 21, wherein the second gate is a floating gate.

29. The method as claimed in claim 21, wherein the first area surrounds the second area and the second area surrounds the third area.

30. The method as claimed in claim 21, during the step of forming the first gate and the second gate in the epitaxial layer, further comprising forming at least one third gate in the epitaxial layer in the third area.

31. The method as claimed in claim 30, wherein the third gate is a floating gate.