MEMORY

• US 20110037119A1
• Filed: 05/13/2009
• Published: 02/17/2011
• Est. Priority Date: 01/05/2009
• Status: Abandoned Application

• Current Assignee: Grace Semiconductor Manufacturing Corporation (Hua Hong Semiconductor Limited)
• Original Assignee: Grace Semiconductor Manufacturing Corporation (Hua Hong Semiconductor Limited)
• Inventors: Kong, Weiran
• Application Number:
  US12/988,125
• Publication Number:
  US 20110037119A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A memory includes: a semiconductor substrate (1), a doped source area (2) and a doped drain area (3) set in the semiconductor substrate (1), and a channel area (4) set between said doped source area (2) and said doped drain area (3); a first insulating layer (5) located on the semiconductor substrate (1), a charge memory layer (6) composed of polysilicon located on said first insulating layer (5); an SiGe conducting layer (7) set in said charge memory layer (6).

Claims

1. A memory, comprising:

a semiconductor substrate;

a doped source area and a drain area, and a channel area between said source area and said drain area, all formed in said semiconductor substrate;

a first insulation layer provided on said semiconductor substrate; and

a charge storage layer made of polysilicon disposed on said first insulation layer,

wherein an Si_1-xGe_x conductor layer is provided in said charge storage layer.

2. The memory as claimed in claim 1, wherein a second insulation layer is disposed on said charge storage layer.

3. The memory as claimed in claim 2, wherein said second insulation layer is made of silicon oxide, silicon nitride, silicon nitrogen oxide, other dielectric layers of high dielectric constants, or any combinations thereof.

4. The memory as claimed in claim 2, wherein a control gate made of polysilicon or other conductive materials is provided on said second insulation layer.

7. The memory as claimed in claim 1, wherein a range of x value for said Si_1-xGe_x conductor layer is 0 to 1.

8. The memory as claimed in claim 1, wherein said charge storage layer is an n-type charge storage layer or a p-type charge storage layer.

9. The memory as claimed in claim 1, wherein said channel area is an n-type channel area or a p-type channel area.

5. The memory as claimed in claim I, wherein said control gate made of polysilicon or other conductive materials is provided on a side of said charge storage layer.

6. The memory as claimed in claim 5, wherein said second insulation layer is used to separate said charge storage layer and said control gate.

10. A memory, comprising:

a semiconductor substrate;

a doped source area and a drain area, and a channel area between said source area and said drain area, all formed in said semiconductor substrate;

a first insulation layer provided on said semiconductor substrate; and

a charge storage layer made of polysilicon disposed on said first insulation layer

wherein, an Si_1-xGe_x conductor layer is provided on said charge storage layer.

11. The memory as claimed in claim 10, wherein a second insulation layer is disposed on said Si_1-xGe_x conductor layer.

12. The memory as claimed in claim 11, wherein a control gate made of polysilicon or other conductive materials is provided on said second insulation layer.

13. The memory as claimed in claim 11 or 12, wherein said second insulation layer is made of silicon oxide, silicon nitride, silicon nitrogen oxide, other dielectric layers of high dielectric constants, or any combinations thereof.

14. The memory as claimed in claim 10, wherein on sides of said charge storage layer and said Si_1-xGe_x conductor layer said control gate made of polysilicon or other conductive materials is provided.

15. The memory as claimed in claim 14, wherein said second insulation layer is used to separate said charge storage layer, said Si_1-xGe_x conductor layer, and said control gate.

16. The memory as claimed in claim 10, wherein a range of x value for said Si_1-xGe_x conductor layer is 0 to 1.

17. The memory as claimed in claim 10, wherein said charge storage layer is an n-type charge storage layer or a p-type charge storage layer.

18. The memory as claimed in claim 10, wherein said channel area is an n-type channel area or a p-type channel area.