INPUT/OUTPUT ELECTROSTATIC DISCHARGE DEVICE WITH REDUCED JUNCTION BREAKDOWN VOLTAGE

• US 20110037121A1
• Filed: 08/16/2009
• Published: 02/17/2011
• Est. Priority Date: 08/16/2009
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Tsao, Wei-Li, Lin, I-Cheng, Lee, Tung-Hsing
• Application Number:
  US12/541,967
• Publication Number:
  US 20110037121A1
• Time in Patent Office: Days
• US Class Current: 257/336
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region, wherein a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region.

Claims

1. An I/O electrostatic discharge (ESD) device, comprising:

a gate electrode over a substrate;

a gate dielectric layer between the gate electrode and the substrate;

a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode;

a first lightly doped drain (LDD) region disposed under one of the sidewall spacers;

a source region disposed next to the first LDD region;

a second LDD region disposed under the other sidewall spacer; and

a drain region disposed next to the second LDD region;

wherein a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region.

2. The I/O ESD device according to claim 1 wherein the first LDD region is an I/O LDD region formed by an LDD implantation process for an I/O device, while the second LDD region is a core LDD region formed by an LDD implantation process for a core device.

3. The I/O ESD device according to claim 1 wherein the first LDD region is an I/O LDD region formed by an LDD implantation process for an I/O device, while the second LDD region is a core+l/O LDD region formed by an LDD implantation process for a core device plus an LDD implantation process for an I/O device.

4. The I/O ESD device according to claim 1, wherein the drain region is coupled to an I/O pad.

5. The I/O ESD device according to claim 1 wherein the gate dielectric layer is formed by a gate dielectric layer for an I/O device.

6. The I/O ESD device according to claim 1 further comprising a pocket region disposed around the second LDD region.

7. The I/O ESD device according to claim 6 wherein the pocket region is formed by a halo implantation performed in the fabrication process for core devices.

8. The I/O ESD device according to claim 1 wherein the first LDD region is an I/O NLDD region and has a junction depth of about 300-1,000 angstroms.

9. The I/O ESD device according to claim 1 wherein the second LDD region is a core NLDD region and has a junction depth of about 200-900 angstroms.

10. The I/O ESD device according to claim 1 further comprising a source salicide layer on the source region.

11. The I/O ESD device according to claim 1 further comprising a drain salicide layer on the drain region with an offset away from an edge of the sidewall spacer to prevent leakage.

12. The I/O ESD device according to claim 1 wherein the first LDD region, the second LDD region, the source region and the drain region are all disposed in an I/O P well.

13. A cascade I/O ESD device, comprising:

a first MOS transistor having a gate electrode, a source structure and a drain structure; and

a second MOS transistor serially connected to the first MOS transistor by sharing the source structure of the first MOS transistor;

wherein the source structure of the first MOS comprises a first lightly doped drain (LDD) region, the drain structure of the first MOS comprises a second LDD region, and a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region.

14. The cascade I/O ESD device according to claim 13 wherein the first LDD region is an I/O LDD region formed by an LDD implantation process for an I/O device, while the second LDD region is a core LDD region formed by an LDD implantation process for a core device.

15. The cascade I/O ESD device according to claim 13 wherein the first LDD region is an I/O LDD region formed by an LDD implantation process for an I/O device, while the second LDD region is a core+I/O LDD region formed by an LDD implantation process for a core device plus an LDD implantation process for an I/O device.

16. The cascade I/O ESD device according to claim 13 wherein the source structure further comprises a source region disposed next to the first LDD region.

17. The cascade I/O ESD device according to claim 13 wherein the drain structure further comprises a drain region disposed next to the second LDD region.

18. The cascade I/O ESD device according to claim 17 wherein the drain region is coupled to an I/O pad.

19. The cascade I/O ESD device according to claim 13 wherein a gate dielectric layer under the gate electrode is formed by a gate dielectric layer for an I/O device.

20. The cascade I/O ESD device according to claim 13 wherein the first and second MOS transistors are both NMOS transistors.

21. The cascade I/O ESD device according to claim 13 wherein the drain structure further comprises a pocket region disposed around the second LDD region.

22. The cascade I/O ESD device according to claim 13 wherein the source structure also functions as a drain of the second MOS transistor.