Semiconductor Device and Method of Forming Dam Material Around Periphery of Die to Reduce Warpage

• US 20110037155A1
• Filed: 08/12/2009
• Published: 02/17/2011
• Est. Priority Date: 08/12/2009
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Pagaila, Reza A.
• Granted Patent: US 8,021,930 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/16 : Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/42 : Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a temporary carrier with a designated area for a first semiconductor die. A dam material is deposited on the carrier around the designated area for a first semiconductor die. The first semiconductor die is mounted to the designated area on the carrier. An encapsulant is deposited over the first semiconductor die and carrier. The dam material is selected to have a CTE that is equal to or less than the CTE of the encapsulant. The carrier is removed to expose the encapsulant and first semiconductor die. A first interconnect structure is formed over the encapsulant. An EMI shielding layer can be formed over the first semiconductor die. A second interconnect structure is formed over a back surface of the first semiconductor die. A conductive pillar is formed between the first and second interconnect structures. A second semiconductor die is mounted to the second interconnect structure.

Claims

1. A method of making a semiconductor device, comprising:

providing a temporary carrier having a designated area for a first semiconductor die;

forming a dam structure on the temporary carrier by depositing dam material on the temporary carrier around the designated area for the first semiconductor die;

mounting the first semiconductor die with its active surface oriented to the designated area on the temporary carrier;

depositing an encapsulant over the first semiconductor die and temporary carrier, the dam material selected to have a coefficient of thermal expansion (CTE) corresponding to a CTE of the encapsulant and a warpage characteristic opposite a warpage characteristic of he encapsulant;

removing the temporary carrier to expose a first side of the encapsulant and active surface of the first semiconductor die, the dam structure stiffening a periphery of the first semiconductor die;

forming a first interconnect structure over the first side of the encapsulant; and

singulating the semiconductor device.

2. The method of claim 1, wherein the CTE of the dam material is equal to or less than the CTE of the encapsulant.

3. The method of claim 1, further including forming a shielding layer over the first semiconductor die.

5. The method of claim 1, further including mounting a heat sink over the encapsulant and first semiconductor die.

6. The method of claim 1, further including:

forming a second interconnect structure over a back surface of the first semiconductor die opposite the active surface of the first semiconductor die;

forming a conductive pillar between the first and second interconnect structures; and

mounting a second semiconductor die to the second interconnect structure.

7. The method of claim 1, further including:

mounting the first semiconductor die so that a portion of the first semiconductor is supported by the dam material; and

forming a bump between a contact pad on the first semiconductor die and first interconnect structure.

26. The method of claim 1, wherein the warpage characteristic of the dam material is concave or convex.

4. (canceled)

8. A method of making a semiconductor device, comprising:

providing a carrier having a designated area for a first semiconductor component;

forming a dam structure on the carrier by depositing dam material on the carrier around the designated area for the first semiconductor component;

mounting the first semiconductor component to the designated area on the carrier;

depositing an encapsulant over the first semiconductor component and carrier, the dam material selected to have a warpage characteristic opposite a warpage characteristic of the encapsulant and stiffening a periphery of the first semiconductor component;

removing the carrier; and

forming a first interconnect structure over the encapsulant.

9. The method of claim 8, wherein a coefficient of thermal expansion (CTE) of the dam material is equal to or less than a CTE of the encapsulant.

11. The method of claim 8, further including forming the dam material up to a top surface of the encapsulant.

12. The method of claim 8, further including mounting a heat sink over the encapsulant and first semiconductor component.

13. The method of claim 8, further including:

forming a second interconnect structure over the first semiconductor component; and

mounting a second semiconductor component to the second interconnect structure.

14. The method of claim 8, further including:

mounting the first semiconductor component so that a portion of the first semiconductor component is supported by the dam material; and

forming a bump between a contact pad on the first semiconductor component and first interconnect structure.

27. The method of claim 8, wherein the warpage characteristic of the dam material is concave or convex.

10. (canceled)

15. A method of making a semiconductor device, comprising:

providing a first semiconductor component;

depositing dam material around a periphery of the first semiconductor component;

depositing an encapsulant over the first semiconductor component, the dam material selected to have a coefficient of thermal expansion (CTE) corresponding to a CTE of the encapsulant;

forming a first interconnect structure over the encapsulant; and

singulating the semiconductor device.

16. The method of claim 15, wherein the CTE of the dam material is equal to or less than the CTE of the encapsulant.

17. The method of claim 15, further including forming a shielding layer around the first semiconductor component.

18. The method of claim 15, further including forming the dam material up to a top surface of the encapsulant.

19. The method of claim 15, further including mounting a heat sink over the encapsulant and first semiconductor component.

20. The method of claim 15, further including:

forming a second interconnect structure over the first semiconductor component; and

mounting a second semiconductor component to the second interconnect structure.

21. A semiconductor device, comprising:

a first semiconductor component;

a dam material deposited around a periphery of the first semiconductor component;

an encapsulant deposited over the first semiconductor component, the dam material selected to have a coefficient of thermal expansion (CTE) corresponding to a CTE of the encapsulant and a warpage characteristic opposite a warpage characteristic of the encapsulant; and

a first interconnect structure formed over the encapsulant.

22. The semiconductor device of claim 21, wherein the CTE of the dam material is equal to or less than the CTE of the encapsulant.

23. The semiconductor device of claim 21, further including a shielding layer formed over the first semiconductor component.

25. The semiconductor device of claim 21, further including:

a second interconnect structure formed over the first semiconductor component; and

a second semiconductor component mounted to the second interconnect structure.

28. The semiconductor device of claim 21, wherein the warpage characteristic of the dam material is concave or convex.

24. (canceled)