SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

• US 20110037166A1
• Filed: 04/08/2009
• Published: 02/17/2011
• Est. Priority Date: 04/09/2008
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Systems Company Limited
• Inventors: Ikeda, Yoshinari, Morozumi, Akira, Takahashi, Yoshikazu, Suzuki, Kenji, Soyano, Shin
• Granted Patent: US 8,450,845 B2
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/29 of an individual layer connector
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29199 Material of the matrix
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29298 Fillers
• CPC Class Codes: H01L 2224/29299 Base material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/40137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 23/051 : another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3735 : Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/473 : by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/49537 : Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/117 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

The object of the present invention is to efficiently dissipate heat from the upper and lower main surfaces of a semiconductor device carrying a semiconductor element. A semiconductor device (1) is provided with an insulating substrate (10A), an insulating substrate (10B) provided so as to face the insulating substrate (10A), and a semiconductor element (20) disposed between the insulating substrate (10A) and the insulating substrate (10B) and having a collector electrode and an emitter electrode provided on the side opposite to that of the collector electrode. The collector electrode is electrically connected to a metal foil (10ac) provided on the insulating substrate (10A), and the emitter electrode is electrically connected to the metal foil (10bc) provided on the insulating substrate (10B). As a result, heat generated by the semiconductor element (20) is efficiently dissipated from the upper and lower main surfaces of the semiconductor device (1).

Claims

1. A semiconductor device comprising:

a first substrate having a first insulating plate, a first metal foil having a portion provided in a region on an inner side from ends of a first main surface of the first insulating plate, and a second metal foil having a portion provided in a region on an inner side from ends of a second main surface of the first insulating plate;

a second substrate having a second insulating plate, a third metal foil having a portion provided in a region on an inner side from ends of a first main surface of the second insulating plate, which is disposed so as to face the first metal foil, and a fourth metal foil having a portion provided in a region on an inner side from ends of a second main surface of the second insulating plate; and

a semiconductor element disposed between the first substrate and the second substrate, and having a first main electrode electrically connected to the first metal foil and a second main electrode electrically connected to the third metal foil; and

a sealing resin that seals the semiconductor element,

wherein the sealing resin covers side surfaces and end surfaces of the first insulating plate on an outer side from the first metal foil and second metal foil, side surfaces and end surfaces of the second insulating plate on the outer side from the third metal foil and fourth metal foil, and side surfaces of the second metal foil and fourth metal foil, and

a main surface of the second metal foil, which is on the side opposite to that of the first insulating plate, and a main surface of the fourth metal foil, which is on the side opposite to that of the second insulating plate, are exposed without the sealing resin.

2. A semiconductor device according to claim 1, wherein a metal member is disposed at least either between the first main electrode and the first metal foil or between the second main electrode and the third metal foil.

3. A semiconductor device according to claim 1, wherein at least one of the second metal foil and the fourth metal foil is thermally connected to a heat dissipating body.

4. A semiconductor device according to claim 3, wherein another semiconductor device is thermally connected to the heat dissipating body.

5. A semiconductor device according to claim 1, further comprising a terminal electrically connected to the semiconductor element and led out to the outside of the sealing resin.

6. A semiconductor device according to claim 5, further comprising:

a third insulating plate; and

a fifth metal foil provided on a first main surface of the third insulating plate and electrically connected to the first metal foil, wherein the terminal is connected to a second main surface of the third insulating plate and electrically connected by a wire to the semiconductor element.

7. A semiconductor device comprising:

a first metal plate;

a second metal plate disposed opposite to the first metal plate;

a semiconductor element disposed between the first and the second metal plates and electrically connected to the first metal plate and the second metal plate;

a first deposited layer with insulating properties formed on a main surface of the first metal plate, which is on a side opposite to that of the semiconductor element; and

a second deposited layer with insulating properties formed on a main surface of the second metal plate, which is on a side opposite to that of the semiconductor element.

8. A semiconductor device according to claim 7, further comprising a sealing resin that seals the semiconductor element,

wherein the sealing resin covers side surfaces of the first metal plate and the second metal plate,

the first deposited layer is formed on a main surface of the first metal plate, which is on a side opposite to that of the semiconductor element and on the sealing resin that covers a side surface of the first metal plate, and

the second deposited layer is formed on a main surface of the second metal plate on a side opposite to that of the semiconductor element, and on the sealing resin that covers a side surface of the second metal plate.

9. A semiconductor device according to claim 7, wherein a heat dissipating body is thermally connected to at least one of the first deposited layer and the second deposited layer.

10. A semiconductor device according to claim 9, wherein another semiconductor device is thermally connected to the heat dissipating body.

11. A method for manufacturing a semiconductor device, comprising:

a step of forming a first substrate by providing a first metal foil and a second metal foil on one main surface of a first insulating plate;

a step of facing a first main electrode, provided on one main surface of a first semiconductor element, to the first metal foil, and electrically connecting the first main electrode and the first metal foil;

a step of facing a second main electrode, provided on one main surface of a second semiconductor element, to the second metal foil, and electrically connecting the second main electrode and the second metal foil;

a step of forming a second substrate by providing a third metal foil and a fourth metal foil on one main surface of a second insulating plate; and

steps of facing a surface side of the second substrate, where the third metal foil and the fourth metal foil are provided, to a surface side of the first substrate, where the first semiconductor element and the second semiconductor element are disposed;

electrically connecting the third metal foil and a third main electrode provided on a main surface of the first semiconductor element, which is on a side opposite to that of the main surface where the first main electrode is provided; and

electrically connecting the fourth metal foil and a fourth main electrode provided on a main surface of the second semiconductor element, which is on a side opposite to that of the main surface where the second main electrode is provided.

12. A method for manufacturing a semiconductor device according to claim 11, further comprising a step of electrically connecting the third main electrode and the second metal foil by using a metal member before facing the first substrate and the second substrate to each other.

13. A method for manufacturing a semiconductor device according to claim 11,

wherein the first substrate has a fifth metal foil provided on a main surface of the first insulating plate, which is on a side opposite to those of the first metal foil and the second metal foil;

the second substrate has a sixth metal foil provided on a main surface of the second insulating plate, which is on a side opposite to those of the third metal foil and the fourth metal foil, and

wherein the method for manufacturing a semiconductor device further comprises, after the step of electrically connecting the third main electrode and the third metal foil and electrically connecting the fourth main electrode and the fourth metal foil, a step of sealing the first semiconductor element and the second semiconductor element and a step of sealing the first insulating plate and the second insulating plates, by using a sealing resin while a main surface of the fifth metal foil, which is on a side opposite to that of the first insulating plate, and a main surface of the sixth metal foil, which is on a side opposite to that of the second insulating plate, are exposed.

14. A method for manufacturing a semiconductor device, comprising:

a step of forming a first substrate by providing a first metal foil and a second metal foil on one main surface of a first insulating plate;

a step of facing a first main electrode, provided on one main surface of a first semiconductor element, to the first metal foil, and electrically connecting the first main electrode and the first metal foil;

a step of forming a second substrate by providing a third metal foil on one main surface of a second insulating plate;

a step of facing a second main electrode, provided on one main surface of a second semiconductor element, to the third metal foil, and electrically connecting the second main electrode and the third metal foil; and

steps of facing a surface side of the second substrate, where the second semiconductor element is disposed, to a surface side of the first substrate, where the first semiconductor element is disposed;

electrically connecting the third metal foil and a third main electrode provided on a main surface of the first semiconductor element, which is on the side opposite to that of the main surface where the first main electrode is provided; and

electrically connecting the second metal foil and a fourth main electrode provided on a main surface of the second semiconductor element, which is on a side opposite to that of the main surface where the second main electrode is provided.

15. A method for manufacturing a semiconductor device according to claim 14,

wherein the first substrate has a fourth metal foil provided on a main surface of the first insulating plate, which is on a side opposite to that of the first metal foil and the second metal foil;

the second substrate has a fifth metal foil provided on a main surface of the second insulating plate, which is on a side opposite to that of the third metal foil, and

wherein the method for manufacturing a semiconductor device further comprises, after the step of electrically connecting the third main electrode and the third metal foil and electrically connecting the fourth main electrode and the second metal foil, a step of sealing the first semiconductor element and the second semiconductor element and the first insulating plate and the second insulating plate by using a sealing resin while a main surface of the fourth metal foil, which is on a side opposite to that of the first insulating plate, and a main surface of the fifth metal foil, which is on a side opposite to that of the second insulating plate, are exposed.

16. A method for manufacturing a semiconductor device, comprising:

a step of forming a substrate by providing a first metal foil on one main surface of a first insulating plate;

a step of facing a first main electrode, provided on one main surface of a first semiconductor element, to face the first metal foil, and electrically connecting the first main electrode and the first metal foil;

a step of facing a second main electrode, provided on one main surface of a second semiconductor element, to the first metal foil, and electrically connecting the second main electrode and the first metal foil;

a step of forming a second substrate by providing a second metal foil on one main surface of a second insulating plate; and

steps of facing a surface side of the second substrate, where the second metal foil is provided, to a surface side of the first substrate, where the first and second semiconductor elements are disposed; and

electrically connecting by using the second metal foil, a third main electrode, which is provided on a main surface of the first semiconductor element on a side opposite to that of the main surface where the first main electrode is provided, and a fourth main electrode, which is provided on a main surface of the second semiconductor element on a side opposite to that of the main surface where the second main electrode is provided.