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TRANSCEIVER AND OPERATING METHOD THEREOF

  • US 20110037505A1
  • Filed: 07/27/2010
  • Published: 02/17/2011
  • Est. Priority Date: 08/17/2009
  • Status: Abandoned Application
First Claim
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1. A transceiver comprising:

  • a clock data recovery circuit;

    a deserializer;

    a serializer;

    a PLL circuit; and

    a frequency detector,wherein the clock data recovery circuit extracts a reproduction clock and reproduction data, in response to a receive signal and a clock signal generated by the PLL circuit,wherein the deserializer serving as a serial-to-parallel converter generates parallel receive data from the reproduction clock and the reproduction data,wherein the serializer serving as a parallel-to-serial converter generates a serial transmit signal from parallel transmit data and the clock signal generated by the PLL circuit,wherein the frequency detector generates a frequency control signal to be supplied to the PLL circuit, by detecting a difference in frequency of the receive signal and the clock signal, andwherein the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency of the receive signal and the clock signal in response to the frequency control signal.

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