TRANSCEIVER AND OPERATING METHOD THEREOF

• US 20110037505A1
• Filed: 07/27/2010
• Published: 02/17/2011
• Est. Priority Date: 08/17/2009
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KAWAMOTO, Takashi
• Application Number:
  US12/843,926
• Publication Number:
  US 20110037505A1
• Time in Patent Office: Days
• US Class Current: 327/159
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A semiconductor chip area is reduced and the possibility of malfunction in generation of reproduction data and a reproduction clock is reduced. A transceiver comprises a clock data recovery circuit, a deserializer, a serializer, a PLL circuit, and a frequency detector. The clock data recovery circuit extracts a reproduction clock and reproduction data in response to a receive signal and a clock signal generated by the PLL circuit. The deserializer generates parallel receive data from the reproduction clock and the reproduction data, and the serializer generates a serial transmit signal from parallel transmit data and the clock signal. The detector detects a difference in frequency of the receive signal and the clock signal, and generates a frequency control signal. In response to the frequency control signal, the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency.

Claims

1. A transceiver comprising:

a clock data recovery circuit;

a deserializer;

a serializer;

a PLL circuit; and

a frequency detector,

wherein the clock data recovery circuit extracts a reproduction clock and reproduction data, in response to a receive signal and a clock signal generated by the PLL circuit,

wherein the deserializer serving as a serial-to-parallel converter generates parallel receive data from the reproduction clock and the reproduction data,

wherein the serializer serving as a parallel-to-serial converter generates a serial transmit signal from parallel transmit data and the clock signal generated by the PLL circuit,

wherein the frequency detector generates a frequency control signal to be supplied to the PLL circuit, by detecting a difference in frequency of the receive signal and the clock signal, and

wherein the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency of the receive signal and the clock signal in response to the frequency control signal.

2. The transceiver according to claim 1,

wherein the PLL circuit comprises:

a waveform generator;

a Σ

Δ

-modulator; and

a variable divider, and

wherein, in response to a waveform signal generated by the waveform generator, the Σ

Δ

-modulator controls a number of average dividing of the variable divider to a value below a decimal point, and the PLL circuit configures a spread spectrum clock generator.

3. The transceiver according to claim 2,

wherein a phase of the clock signal generated by the PLL circuit is controlled by supplying the frequency control signal generated by the frequency detector to the waveform generator of the PLL circuit.

4. The transceiver according to claim 3,

wherein, by detecting the difference in frequency of the receive signal and the clock signal, the frequency detector generates a modulation cycle adjustment signal and a degree-of-modulation adjustment signal which are supplied to the PLL circuit, and

wherein, in response to the modulation cycle adjustment signal and the degree-of-modulation adjustment signal, the PLL circuit controls the cycle and degree of modulation of the clock signal so as to reduce the difference in frequency of the receive signal and the clock signal.

5. The transceiver according to claim 1,

wherein the clock data recovery circuit comprises:

a phase comparator;

an integrator;

a phase selection unit; and

a clock selection unit,

wherein the clock selection unit is supplied with the multiphase clock signal generated by the PLL circuit and a pointer value generated by the phase selection unit, and generates a plurality of selection clock output signals from the multiphase clock signal, in response to the pointer value,

wherein the phase comparator is supplied with the receive signal and the plural selection clock output signals generated by the clock selection unit, and generates an early phase signal and a late phase signal, in response to relation between a phase of the receive signal and plural phases of the plural selection clock output signals,

wherein the integrator is supplied with the early phase signal and the late phase signal which are generated by the phase comparator, and generates an “

up”

signal and a “

down”

signal, and

wherein the clock selection unit is supplied with the “

up”

signal and the “

down”

signal which are generated by the integrator, and a value of the pointer value generated by the clock selection unit is set up.

6. The transceiver according to claim 5,

wherein the clock data recovery circuit, the deserializer, the serializer, the PLL circuit, and the frequency detector are formed in a semiconductor integrated circuit.

7. The transceiver according to claim 5,

wherein the waveform signal generated by the waveform generator of the PLL circuit is a triangular-wave signal.

8. An operating method for a transceiver which comprises:

a clock data recovery circuit;

a deserializer;

a serializer;

a PLL circuit; and

a frequency detector,

wherein the clock data recovery circuit extracts a reproduction clock and reproduction data, in response to a receive signal and a clock signal generated by the PLL circuit,

wherein the deserializer serving as a serial-to-parallel converter generates parallel receive data from the reproduction clock and the reproduction data,

wherein the serializer serving as a parallel-to-serial converter generates a serial transmit signal from parallel transmit data and the clock signal generated by the PLL circuit,

wherein the frequency detector generates a frequency control signal to be supplied to the PLL circuit, by detecting a difference in frequency of the receive signal and the clock signal, and

wherein the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency of the receive signal and the clock signal in response to the frequency control signal.

9. The operating method for the transceiver according to claim 8,

wherein the PLL circuit comprises:

a waveform generator;

a Σ

Δ

-modulator; and

a variable divider, and

wherein, in response to a waveform signal generated by the waveform generator, the Σ

Δ

-modulator controls a number of average dividing of the variable divider to a value below a decimal point, and the PLL circuit configures a spread spectrum clock generator.

10. The operating method for the transceiver according to claim 9,

wherein a phase of the clock signal generated by the PLL circuit is controlled, by supplying the frequency control signal generated by the frequency detector to the waveform generator of the PLL circuit.

11. The operating method for the transceiver according to claim 10,

wherein, by detecting the difference in frequency of the receive signal and the clock signal, the frequency detector generates a modulation cycle adjustment signal and a degree-of-modulation adjustment signal which are supplied to the PLL circuit, and

wherein, in response to the modulation cycle adjustment signal and the degree-of-modulation adjustment signal, the PLL circuit controls the cycle and degree of modulation of the clock signal so as to reduce the difference in frequency of the receive signal and the clock signal.

12. The operating method for the transceiver according to claim 8,

wherein the clock data recovery circuit comprises:

a phase comparator;

an integrator;

a phase selection unit; and

a clock selection unit,

wherein the clock selection unit is supplied with the multiphase clock signal generated by the PLL circuit and a pointer value generated by the phase selection unit, and generates a plurality of selection clock output signals from the multiphase clock signal, in response to the pointer value,

wherein the phase comparator is supplied with the receive signal and the plural selection clock output signals generated by the clock selection unit, and generates an early phase signal and a late phase signal, in response to relation between a phase of the receive signal and plural phases of the plural selection clock output signals,

wherein the integrator is supplied with the early phase signal and the late phase signal which are generated by the phase comparator, and generates an “

up”

signal and a “

down”

signal, and

wherein the clock selection unit is supplied with the “

up”

signal and the “

down”

signal which are generated by the integrator, and a value of the pointer value generated by the clock selection unit is set up.

13. The operating method for the transceiver according to claim 12,

wherein the clock data recovery circuit, the deserializer, the serializer, the PLL circuit, and the frequency detector are formed in a semiconductor integrated circuit.

14. The operating method for the transceiver according to claim 12,

wherein the waveform signal generated by the waveform generator of the PLL circuit is a triangular-wave signal.