TRANSCEIVER AND OPERATING METHOD THEREOF
First Claim
1. A transceiver comprising:
- a clock data recovery circuit;
a deserializer;
a serializer;
a PLL circuit; and
a frequency detector,wherein the clock data recovery circuit extracts a reproduction clock and reproduction data, in response to a receive signal and a clock signal generated by the PLL circuit,wherein the deserializer serving as a serial-to-parallel converter generates parallel receive data from the reproduction clock and the reproduction data,wherein the serializer serving as a parallel-to-serial converter generates a serial transmit signal from parallel transmit data and the clock signal generated by the PLL circuit,wherein the frequency detector generates a frequency control signal to be supplied to the PLL circuit, by detecting a difference in frequency of the receive signal and the clock signal, andwherein the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency of the receive signal and the clock signal in response to the frequency control signal.
1 Assignment
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Accused Products
Abstract
A semiconductor chip area is reduced and the possibility of malfunction in generation of reproduction data and a reproduction clock is reduced. A transceiver comprises a clock data recovery circuit, a deserializer, a serializer, a PLL circuit, and a frequency detector. The clock data recovery circuit extracts a reproduction clock and reproduction data in response to a receive signal and a clock signal generated by the PLL circuit. The deserializer generates parallel receive data from the reproduction clock and the reproduction data, and the serializer generates a serial transmit signal from parallel transmit data and the clock signal. The detector detects a difference in frequency of the receive signal and the clock signal, and generates a frequency control signal. In response to the frequency control signal, the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency.
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Citations
14 Claims
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1. A transceiver comprising:
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a clock data recovery circuit; a deserializer; a serializer; a PLL circuit; and a frequency detector, wherein the clock data recovery circuit extracts a reproduction clock and reproduction data, in response to a receive signal and a clock signal generated by the PLL circuit, wherein the deserializer serving as a serial-to-parallel converter generates parallel receive data from the reproduction clock and the reproduction data, wherein the serializer serving as a parallel-to-serial converter generates a serial transmit signal from parallel transmit data and the clock signal generated by the PLL circuit, wherein the frequency detector generates a frequency control signal to be supplied to the PLL circuit, by detecting a difference in frequency of the receive signal and the clock signal, and wherein the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency of the receive signal and the clock signal in response to the frequency control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An operating method for a transceiver which comprises:
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a clock data recovery circuit; a deserializer; a serializer; a PLL circuit; and a frequency detector, wherein the clock data recovery circuit extracts a reproduction clock and reproduction data, in response to a receive signal and a clock signal generated by the PLL circuit, wherein the deserializer serving as a serial-to-parallel converter generates parallel receive data from the reproduction clock and the reproduction data, wherein the serializer serving as a parallel-to-serial converter generates a serial transmit signal from parallel transmit data and the clock signal generated by the PLL circuit, wherein the frequency detector generates a frequency control signal to be supplied to the PLL circuit, by detecting a difference in frequency of the receive signal and the clock signal, and wherein the PLL circuit controls a cycle of the clock signal so as to reduce the difference in frequency of the receive signal and the clock signal in response to the frequency control signal. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification