APPARATUS AND METHOD FOR EFFICIENT LEVEL SHIFT

• US 20110037509A1
• Filed: 08/12/2010
• Published: 02/17/2011
• Est. Priority Date: 08/13/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments Deutschland Gesellschaft Mit Beschrã¤Nkter Haftung (Texas Instruments, Inc.)
• Inventors: Stettner, Ferdinand, Wicht, Bernhard, Herzer, Stefan
• Granted Patent: US 8,013,655 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element.

Claims

1. An apparatus comprising:

an input stage having a first branch and a second branch;

a first flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first flip-flop that is coupled to the first branch, and wherein the second input terminal of the first flip-flop is coupled to the second branch, and wherein the first flip-flop operates in a first voltage domain;

a level shifter that is coupled to the output terminal of the first flip-flop, wherein the level shifter operates in a second voltage domain, and wherein the level shifter includes;

a reset stage having a first capacitor that is coupled to the output terminal of the first flip-flop;

a set stage having a second capacitor that is coupled to the output terminal of the first flip-flop; and

a second flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second flip-flop is coupled to the reset stage, and wherein the second input terminal of the second flip-flop is coupled to the set stage; and

a logic circuit that is coupled to the output terminal of the second flip-flop, the first branch, and the second branch, and that receives an input signal.

2. The apparatus of claim 1, wherein the apparatus further comprises the first-flop is an active low flip-flop.

3. The apparatus of claim 2, wherein the first branch further comprises:

a first resistor that receives a first voltage from the first voltage domain and that is coupled to the first input terminal of the first flip-flop; and

a first MOS transistor that is coupled to the first resistor at its drain and that is coupled to the logic circuit at its gate.

4. The apparatus of claim 3, wherein the second branch further comprises:

a second resistor that receives the first voltage from the first voltage domain and that is coupled to the second input terminal of the first flip-flop; and

a second MOS transistor that is coupled to the second resistor at its drain and that is coupled to the logic circuit at its gate.

5. The apparatus of claim 4, wherein the logic circuit further comprises:

an AND gate that is coupled to the output terminal of the second flip-flop and to the gate of the second MOS transistor and that receives the input signal; and

a NOR gate that is coupled to the output terminal of the second flip-flop and to the gate of the first MOS transistor and that receives the input signal.

6. The apparatus of claim 5, wherein the reset stage further comprises an inverter that is coupled between the first capacitor and the first input terminal of the second flip-flop.

7. The apparatus of claim 6, wherein the set stage further comprises a plurality of inverters coupled in series with one another between the second capacitor and the second input terminal of the second flip-flop.

8. An apparatus comprising:

a high voltage rail;

a low voltage rail;

a control circuit having a first output terminal and a second output terminal, wherein the control circuit is coupled to the low voltage rail;

a level shifter having;

an input stage having a first branch and a second branch that are each coupled to the high voltage rail;

a first flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first flip-flop that is coupled to the first branch, and wherein the second input terminal of the first flip-flop is coupled to the second branch, and wherein the first flip-flop is coupled to the high voltage rail;

a reset stage having a first capacitor that is coupled to the output terminal of the first flip-flop, wherein the reset stage is coupled to the low voltage rail;

a set stage having a second capacitor that is coupled to the output terminal of the first flip-flop, wherein the set stage is coupled to the low voltage rail; and

a second flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second flip-flop is coupled to the rest stage, and wherein the second input terminal of the second flip-flop is coupled to the set stage, and wherein the second flip-flop is coupled to the low voltage rail; and

a logic circuit that is coupled to the output terminal of the second flip-flop, the first branch, the second branch, and the first output terminal of the control circuit;

a high side driver that is coupled to the output terminal of the first flip-flop;

a low side driver that is coupled to the second output terminal of the control circuit;

a current sensing circuit that is adapted to receive a current feedback signal;

an error amplifier that is adapted to receive a voltage feedback signal; and

a summing comparator that is coupled to the current sensing circuit, the voltage sensing circuit, and the control circuit.

9. The apparatus of claim 8, wherein the apparatus further comprises the first-flop is an active low flip-flop.

10. The apparatus of claim 9, wherein the first branch further comprises:

a first resistor that is coupled to the first input terminal of the first flip-flop and the high voltage rail; and

a first MOS transistor that is coupled to the first resistor at its drain and that is coupled to the logic circuit at its gate.

11. The apparatus of claim 10, wherein the second branch further comprises:

a second resistor that is coupled to the second input terminal of the first flip-flop and the high voltage rail; and

a second MOS transistor that is coupled to the second resistor at its drain and that is coupled to the logic circuit at its gate.

12. The apparatus of claim 11, wherein the logic circuit further comprises:

an AND gate that is coupled to the output terminal of the second flip-flop, the gate of the second MOS transistor, and the first output terminal of the control circuit; and

a NOR gate that is coupled to the output terminal of the second flip-flop, the gate of the first MOS transistor and that receives the input signal, and the first output terminal of the control circuit.

13. The apparatus of claim 12, wherein the reset stage further comprises an inverter that is coupled between the first capacitor and the first input terminal of the second flip-flop.

14. The apparatus of claim 13, wherein the set stage further comprises a plurality of inverters coupled in series with one another between the second capacitor and the second input terminal of the second flip-flop.

15. The apparatus of claim 8, wherein the apparatus further comprises:

a high side switch that is coupled to the high side driver and a switching node;

a low side switch that is coupled to the low side driver and the switching node;

an inductor that is coupled to the switching node;

a resistor-capacitor (RC) network that is coupled in parallel to the inductor, wherein the RC network is coupled to the current sensing circuit; and

a voltage divider that is coupled to the inductor and the error amplifier.

16. An apparatus comprising:

a high voltage rail;

a low voltage rail;

an input stage having;

a first resistor that is coupled to the high voltage rail;

a first MOS transistor that is coupled to the first resistor at its drain;

a second resistor that is coupled to the high voltage rail; and

a second MOS transistor that is coupled to the second resistor at its drain;

a first flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first flip-flop that is coupled to the first resistor, and wherein the second input terminal of the first flip-flop is coupled to the second resistor, and wherein the first flip-flop is coupled to the high voltage rail;

a reset stage having a first capacitor that is coupled to the output terminal of the first flip-flop, wherein the reset stage is coupled to the low voltage rail;

a set stage having a second capacitor that is coupled to the output terminal of the first flip-flop, wherein the set stage is coupled to the low voltage rail; and

a second flip-flop having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the second flip-flop is coupled to the rest stage, and wherein the second input terminal of the second flip-flop is coupled to the set stage, and wherein the second flip-flop is coupled to the low voltage rail; and

a logic circuit that is coupled to the output terminal of the second flip-flop, the first branch, the second branch, and that receives an input signal.

17. The apparatus of claim 16, wherein the logic circuit further comprises:

an AND gate that is coupled to the output terminal of the second flip-flop and to the gate of the second MOS transistor and that receives the input signal; and

a NOR gate that is coupled to the output terminal of the second flip-flop and to the gate of the first MOS transistor and that receives the input signal.

18. The apparatus of claim 17, wherein the reset stage further comprises an inverter that is coupled between the first capacitor and the first input terminal of the second flip-flop.

19. The apparatus of claim 18, wherein the set stage further comprises a plurality of inverters coupled in series with one another between the second capacitor and the second input terminal of the second flip-flop.

20. The apparatus of claim 19, wherein the apparatus further comprises:

a first charge injection stage having;

a third MOS transistor, wherein the third MOS transistor matches the first MOS transistor; and

a first current mirror that is coupled to the high voltage rail, the third MOS transistor, and a node between the first resistor and the first MOS transistor; and

a second charge injection stage having;

a fourth MOS transistor, wherein the fourth MOS transistor matches the second MOS transistor; and

a second current minor that is coupled to the high voltage rail, the fourth MOS transistor, and a node between the second resistor and the second MOS transistor.