AMPLIFIERS WITH IMPROVED LINEARITY AND NOISE PERFORMANCE

• US 20110037518A1
• Filed: 08/11/2009
• Published: 02/17/2011
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chang, Li-chung, Lee, Hanil
• Granted Patent: US 8,310,312 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/492 A coil being added in the source circuit of a transistor amplifier stage as degenerating element
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/45302 the common gate stage of a cascode dif amp being controlled
• CPC Class Codes: H03F 2203/45311 the common gate stage of a cascode dif amp being implemented by multiple transistors
• CPC Class Codes: H03F 2203/45386 the AAC comprising one or more coils in the source circuit
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input

Abstract

Amplifiers with improved linearity and noise performance are described. In an exemplary design, an apparatus includes first through sixth transistors. The first transistor receives an input signal and provides an amplified signal. The second transistor receives the amplified signal and provides signal drive for an output signal. The third transistor receives the input signal and provides an intermediate signal. The fourth transistor provides bias for the third transistor in a high linearity mode. The fifth transistor receives the intermediate signal and provides signal drive for the output signal in a low linearity mode. The third and fourth transistors form a deboost path that is enabled in the high linearity mode to improve linearity. The third and fifth transistors form a cascode path that is enabled in the low linearity mode to improve gain and noise performance. The sixth transistor generates distortion component used to cancel distortion component from the first transistor.

Claims

1. An apparatus comprising:

a first transistor receiving an input signal and providing an amplified signal;

a second transistor coupled to the first transistor, the second transistor receiving the amplified signal and providing signal drive for an output signal;

a third transistor coupled to the first transistor, the third transistor receiving the input signal and providing an intermediate signal;

a fourth transistor coupled to the third transistor and providing bias for the third transistor in a high linearity mode; and

a fifth transistor coupled to the third transistor, the fifth transistor receiving the intermediate signal and providing signal drive for the output signal in a low linearity mode.

2. The apparatus of claim 1, the fourth transistor being enabled in the high linearity mode and disabled in the low linearity mode, and the fifth transistor being enabled in the low linearity mode and disabled in the high linearity mode.

3. The apparatus of claim 1, further comprising:

a sixth transistor coupled to the first transistor and generating distortion component used to cancel distortion component generated by the first transistor.

4. The apparatus of claim 3, the sixth transistor having a gate receiving the input signal and a drain coupled to a drain of the first transistor.

5. The apparatus of claim 3, the sixth transistor being enabled in the high linearity mode and disabled in the low linearity mode.

6. The apparatus of claim 1, further comprising:

an inductor coupled to a source of the first transistor and providing source degeneration for the first transistor.

7. The apparatus of claim 6, the third transistor providing more current through the inductor to increase inductance of the inductor and improve linearity of the first transistor in the high linearity mode.

8. The apparatus of claim 3, further comprising:

a first inductor coupled to a source of the first transistor and providing source degeneration for the first transistor; and

a second inductor coupled to a source of the sixth transistor and providing source degeneration for the sixth transistor.

9. The apparatus of claim 1, further comprising:

a load coupled to the second and fifth transistors and comprising an inductor and a capacitor coupled in parallel.

10. The apparatus of claim 1, further comprising:

a transformer comprising a primary coil and a secondary coil, the primary coil being coupled to the second and fifth transistors, and the secondary coil being coupled to a subsequent circuit.

11. The apparatus of claim 1, the input signal observing similar input impedance in the high linearity mode and the low linearity mode.

12. The apparatus of claim 1, further comprising:

a sixth transistor receiving a complementary input signal and providing a complementary amplified signal;

a seventh transistor coupled to the sixth transistor, the seventh transistor receiving the complementary amplified signal and providing signal drive for a complementary output signal;

an eight transistor receiving the complementary input signal and providing a complementary intermediate signal;

a ninth transistor coupled to the eight transistor and providing bias for the eight transistor in the high linearity mode; and

a tenth transistor coupled to the eight transistor, the tenth transistor receiving the complementary intermediate signal and providing signal drive for the complementary output signal in the low linearity mode.

13. The apparatus of claim 1, further comprising:

a jammer detector to detect for jammers in the input signal, the high and low linearity modes being determined based on detected jammers in the input signal.

14. An apparatus comprising:

an amplifier to receive an input signal and provide an output signal, the amplifier comprising;

a main signal path receiving and amplifying the input signal and providing the output signal; and

an auxiliary signal path coupled in parallel with the main signal path and comprising a first path and a second path, the first path being enabled to improve linearity of the amplifier, the second path being enabled to improve gain and noise performance of the amplifier, the first and second paths sharing a common source transistor.

15. The apparatus of claim 14, the main signal path comprising

a first transistor receiving the input signal and providing an amplified signal, and

a second transistor coupled to the first transistor, the second transistor receiving the amplified signal and providing signal drive for the output signal.

16. The apparatus of claim 14, the auxiliary signal path comprising

a first transistor receiving the input signal and providing an intermediate signal, the first transistor being the common source transistor,

a second transistor coupled to the first transistor, the second transistor providing bias for the first transistor in a high linearity mode to improve the linearity of the amplifier, the first path comprising the first and second transistors, and

a third transistor coupled to the first transistor, the third transistor receiving the intermediate signal and providing signal drive for the output signal in a low linearity mode to improve the gain and noise performance of the amplifier, the second path comprising the first and third transistors.

17. The apparatus of claim 14, the amplifier further comprising:

a distortion generation path coupled in parallel with the main signal path, the distortion generation path generating distortion component used to cancel distortion component generated by the main signal path.

18. The apparatus of claim 14, the amplifier further comprising:

a second auxiliary signal path coupled in parallel with the main signal path and comprising a third path and a fourth path, the third path being enabled to improve the linearity of the amplifier, the fourth path being enabled to improve the gain and noise performance of the amplifier, the third and fourth paths sharing a second common source transistor.

19. The apparatus of claim 14, further comprising:

a second amplifier to receive a second input signal and provide a second output signal, the amplifier and the second amplifier having outputs coupled together; and

a transformer having a primary coil and a secondary coil, the primary coil having one end coupled to the outputs of the amplifier and the second amplifier.

20. A wireless communication device comprising:

an antenna providing an input radio frequency (RF) signal; and

a low noise amplifier (LNA) amplifying the input RF signal and providing an output RF signal, the LNA comprising

a first transistor receiving the input RF signal and providing an amplified signal;

a second transistor coupled to the first transistor, the second transistor receiving the amplified signal and providing signal drive for the output RF signal;

a third transistor coupled to the first transistor, the third transistor receiving the input RF signal and providing an intermediate signal;

a fourth transistor coupled to the third transistor and providing bias for the third transistor in a high linearity mode; and

a fifth transistor coupled to the third transistor, the fifth transistor receiving the intermediate signal and providing signal drive for the output RF signal in a low linearity mode.

21. The wireless communication device of claim 20, the LNA further comprising a sixth transistor coupled to the first transistor and generating distortion component used to cancel distortion component generated by the first transistor in the high linearity mode.

22. A method of performing signal amplification, comprising:

amplifying an input signal with a first transistor to obtain an amplified signal;

buffering the amplified signal with a second transistor to obtain an output signal;

amplifying the input signal with a third transistor to obtain an intermediate signal;

providing bias for the third transistor with a fourth transistor in a high linearity mode; and

buffering the intermediate signal and providing signal drive for the output signal with a fifth transistor in a low linearity mode.

23. The method of claim 22, further comprising:

generating distortion component with a sixth transistor in the high linearity mode; and

canceling distortion component generated by the first transistor with the distortion component generated by the sixth transistor in the high linearity mode.

24. The method of claim 22, further comprising:

enabling the fourth transistor in the high linearity mode;

disabling the fourth transistor in the low linearity mode;

enabling the fifth transistor in the low linearity mode; and

disabling the fifth transistor in the high linearity mode.

25. An apparatus comprising:

means for amplifying an input signal to obtain an amplified signal;

means for buffering the amplified signal to obtain an output signal;

means for amplifying the input signal to obtain an intermediate signal;

means for providing bias to the means for amplifying the input signal to obtain the intermediate signal in a high linearity mode; and

means for buffering the intermediate signal and providing signal drive for the output signal in a low linearity mode.