GUARDED ELECTRICAL OVERSTRESS PROTECTION CIRCUIT

• US 20110038083A1
• Filed: 12/24/2009
• Published: 02/17/2011
• Est. Priority Date: 08/17/2009
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: COLN, Michael, CARREAU, Gary, KUSUDA, Yoshinori
• Granted Patent: US 8,837,099 B2
• Time in Patent Office: Days
• US Class Current: 361/54
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.

Claims

1. An electrical overstress protection circuit, comprising:

a pair of clamp devices, having opposite polarity, connecting an input signal line to a common node; and

a second pair of clamp devices, each extending from the common node to a respective reference potential source.

2. The electrical overstress protection circuit of claim 1, wherein the clamp devices are diodes.

3. The electrical overstress protection circuit according to claim 1, further comprising a third reference potential source coupled to the common node, having a voltage equal to an expected DC voltage of a data signal to be input on the input signal line.

4. The electrical overstress protection circuit of claim 3, wherein the input data signal is a time-varying current signal.

5. The electrical overstress protection circuit of claim 3, wherein the input data signal is a time-varying voltage signal.

6. The electrical overstress protection circuit of claim 1, further comprising a plurality of input data signal lines, each data signal line connected to a plurality of clamping devices clamping each input signal line to the intermediate node.

7. The electrical overstress protection circuit of claim 1, further comprising a test circuit clamped to the intermediate node, the test circuit comprising a switch for connecting the test circuit to the intermediate node and a test signal input receiver for receiving a test input data signal.

8. The electrical overstress protection circuit of claim 1, further comprising an RC network extending from the reference voltage through the intermediate node to one of the first and second reference potentials.

9. A data receiver including an electrical overstress protection circuit, comprising:

an input signal line to receive an input data signal; and

a clamp circuit receiving a reference voltage at an intermediate node, comprising;

a plurality of clamp devices clamping the input signal line to the intermediate node,

a clamp device clamping the intermediate node to a first reference potential, and

a clamp device clamping the intermediate node to a second reference potential,

10. The data receiver of claim 9, further comprising:

an RC network extending from the reference voltage through the intermediate node to the second reference potentials.

11. The data receiver of claim 9, wherein the reference voltage is equal to a DC offset voltage component of the input data signal.

12. The data receiver of claim 9, wherein the clamp devices are diodes.

13. The data receiver of claim 9, wherein the input signal is a time-varying current signal.

14. The data receiver of claim 9, wherein the input signal is a time-varying voltage signal.

15. The data receiver of claim 9, further comprising:

a circuit device connected between the input signal and to the intermediate node that derives the reference voltage based upon the input data signal.

16. The data receiver of claim 9, further comprising:

a plurality of inputs for receiving input data signals; and

a plurality of clamping devices clamping each input signal line to the intermediate node.

17. The data receiver of claim 9, further comprising:

a test circuit connected to the intermediate node.

18. The data receiver of claim 17, the test circuit comprising:

a switch for connecting the test circuit to the intermediate node; and

a test signal outputting a test data signal.

19. An overstress protection circuit for an input signal line of an integrated circuit, comprising:

a two-stage clamping circuit coupling the input signal line to a pair of reference potential sources, a first stage of the clamping circuit extending from the input signal line to an intermediate node and a second stage of the clamping circuit extending from the intermediate node to at least one reference potential, and

a signal source providing a signal equal to the input signal to the intermediate node.

20. The overstress protection circuit of claim 19, further comprising:

a filter extending from the input signal line through the intermediate node to one of the first and second reference potentials.