METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A BUMP/BASE HEAT SPREADER AND A CAVITY IN THE BUMP

• US 20110039374A1
• Filed: 10/28/2010
• Published: 02/17/2011
• Est. Priority Date: 03/25/2008
• Status: Abandoned Application

• Current Assignee: Bridge Semiconductor Corporation
• Original Assignee: Bridge Semiconductor Corporation
• Inventors: Lin, Charles W.C., Wang, Chia-Chung
• Application Number:
  US12/913,762
• Publication Number:
  US 20110039374A1
• Time in Patent Office: Days
• US Class Current: 438/118
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/0665 Epoxy resin
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 33/483 : Containers
• CPC Class Codes: H01L 33/642 : characterized by the shape
• CPC Class Codes: H05K 1/021 : Components thermally connected to metal substrates or heat-sinks by insert mounting
• CPC Class Codes: H05K 2201/0352 : Differences between the conductors of different layers of a multilayer
• CPC Class Codes: H05K 2201/0355 : Metal foils
• CPC Class Codes: H05K 2201/10106 : Light emitting diode [LED]
• CPC Class Codes: H05K 2203/049 : Wire bonding
• CPC Class Codes: H05K 2203/063 : of preperforated insulating layer
• CPC Class Codes: H05K 3/4084 : by deforming at least one of the conductive layers

Abstract

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump, a base and a flange. The conductive trace includes a pad and a terminal. The semiconductor device extends into a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Claims

1-85. -85. (canceled)

86. A method of making a semiconductor chip assembly, comprising:

providing a bump, a ledge, an adhesive and a conductive layer, wherein

the bump defines a cavity that faces in a first vertical direction and has an entrance at the ledge, and the bump is adjacent to and integral with the ledge, extends vertically from the ledge in a second vertical direction opposite the first vertical direction, extends into an opening in the adhesive and is aligned with an aperture in the conductive layer,

the ledge extends laterally from the bump in lateral directions orthogonal to the vertical directions,

the adhesive is mounted on the ledge, is sandwiched between the ledge and the conductive layer and is non-solidified, and

the conductive layer is mounted on the adhesive;

then

flowing the adhesive in the second vertical direction into a gap located in the aperture between the bump and the conductive layer;

solidifying the adhesive;

then

providing a conductive trace that includes a pad, a terminal and a selected portion of the ledge that is spaced from the bump;

providing a heat spreader that includes the bump, a base and a flange, wherein the bump is adjacent to the base and extends vertically from the base in the first vertical direction, the base extends vertically from the bump in the second vertical direction and the flange includes a selected portion of the ledge that is adjacent to and integral with and extends laterally from the bump;

then

mounting a semiconductor device on the bump, wherein the semiconductor device extends into the cavity;

electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and

thermally connecting the semiconductor device to the bump, thereby thermally connecting the semiconductor device to the base.

87. The method of claim 86, wherein providing the bump includes mechanically stamping a metal plate.

88. The method of claim 86, wherein:

providing the adhesive includes providing a prepreg with uncured epoxy;

flowing the adhesive includes melting the uncured epoxy and compressing the uncured epoxy between the ledge and the conductive layer; and

solidifying the adhesive includes curing the uncured epoxy.

89. The method of claim 86, wherein flowing the adhesive includes filling the gap with the adhesive.

90. The method of claim 86, wherein mounting the conductive layer includes mounting the conductive layer alone on the adhesive.

91. The method of claim 86, wherein mounting the conductive layer includes mounting the conductive layer and a dielectric layer on the adhesive.

92. The method of claim 86, wherein providing the pad includes removing selected portions of the ledge after solidifying the adhesive.

93. The method of claim 86, wherein providing the terminal includes removing selected portions of the conductive layer after solidifying the adhesive.

94. The method of claim 86, wherein providing the terminal includes:

grinding the bump, the adhesive and the conductive layer such that the bump, the adhesive and the conductive layer are laterally aligned with one another at a lateral surface that faces in the second vertical direction; and

then

removing selected portions of the conductive layer using an etch mask that defines the terminal.

95. The method of claim 86, wherein mounting the semiconductor device includes providing a die attach between the semiconductor device and the bump, electrically connecting the semiconductor device includes providing a wire bond between the semiconductor device and the pad, and thermally connecting the semiconductor device includes providing the die attach between the semiconductor device and the bump.

96. A method of making a semiconductor chip assembly, comprising:

providing a bump and a ledge, wherein the bump defines a cavity that faces in a first vertical direction and has an entrance at the ledge, the bump is adjacent to and integral with the ledge and extends vertically from the ledge in a second vertical direction opposite the first vertical direction and the ledge extends laterally from the bump in lateral directions orthogonal to the vertical directions;

providing an adhesive, wherein an opening extends through the adhesive;

providing a conductive layer, wherein an aperture extends through the conductive layer;

mounting the adhesive on the ledge, wherein the bump extends into the opening;

mounting the conductive layer on the adhesive, including aligning the bump with the aperture, wherein the adhesive is sandwiched between the ledge and the conductive layer and is non-solidified;

then

applying heat to melt the adhesive;

moving the ledge and the conductive layer towards one another, thereby moving the bump in the second vertical direction in the aperture and applying pressure to the molten adhesive between the ledge and the conductive layer, wherein the pressure forces the molten adhesive to flow in the second vertical direction into a gap located in the aperture between the bump and the conductive layer;

applying heat to solidify the molten adhesive, thereby mechanically attaching the bump and the ledge to the conductive layer;

then

providing a conductive trace that includes a pad, a terminal and selected portions of the ledge and the conductive layer that are spaced from the bump;

providing a heat spreader that includes the bump, a base and a flange, wherein the bump is adjacent to the base and extends vertically from the base in the first vertical direction, the base extends vertically from the bump in the second vertical direction and extends laterally from the bump and the flange includes a selected portion of the ledge that is adjacent to and integral with and extends laterally from the bump;

then

mounting a semiconductor device on the bump, wherein the semiconductor device extends into the cavity;

electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and

thermally connecting the semiconductor device to the bump, thereby thermally connecting the semiconductor device to the base.

97. The method of claim 96, wherein providing the bump includes mechanically stamping a metal plate.

98. The method of claim 96, wherein:

providing the adhesive includes providing a prepreg with uncured epoxy;

flowing the adhesive includes melting the uncured epoxy and compressing the uncured epoxy between the ledge and the conductive layer; and

solidifying the adhesive includes curing the uncured epoxy.

99. The method of claim 96, wherein flowing the adhesive includes filling the gap with the adhesive.

100. The method of claim 96, wherein mounting the conductive layer includes mounting the conductive layer alone on the adhesive.

101. The method of claim 96, wherein mounting the conductive layer includes mounting the conductive layer and a dielectric layer on the adhesive.

102. The method of claim 96, wherein providing the pad includes removing selected portions of the ledge using an etch mask that defines the pad after solidifying the adhesive.

103. The method of claim 96, wherein providing the terminal includes removing selected portions of the conductive layer using an etch mask that defines the terminal after solidifying the adhesive.

104. The method of claim 96, wherein providing the terminal includes:

grinding the bump, the adhesive and the conductive layer such that the bump, the adhesive and the conductive layer are laterally aligned with one another at a lateral surface that faces in the second vertical direction; and

then

removing selected portions of the conductive layer using an etch mask that defines the terminal.

105. The method of claim 96, wherein mounting the semiconductor device includes providing a die attach between the semiconductor device and the bump, electrically connecting the semiconductor device includes providing a wire bond between the semiconductor device and the pad, and thermally connecting the semiconductor device includes providing the die attach between the semiconductor device and the bump.

106. A method of making a semiconductor chip assembly, comprising:

providing a bump, a ledge, an adhesive and a substrate, wherein

the bump defines a cavity that faces in a first vertical direction and has an entrance at the ledge, and the bump is adjacent to and integral with the ledge, extends vertically from the ledge in a second vertical direction opposite the first vertical direction, extends into an opening in the adhesive and is aligned with an aperture in the substrate,

the ledge extends laterally from the bump in lateral directions orthogonal to the vertical directions,

the adhesive is mounted on the ledge, is sandwiched between the ledge and the substrate and is non-solidified, and

the substrate is mounted on the adhesive, wherein the substrate includes a conductive layer and a dielectric layer and the dielectric layer is sandwiched between the conductive layer and the adhesive;

then

flowing the adhesive in the second vertical direction into a gap located in the aperture between the bump and the conductive layer;

solidifying the adhesive;

then

providing a conductive trace that includes a pad, a terminal, a plated through-hole, a selected portion of the ledge that is adjacent to the plated through-hole and spaced from the bump and a selected portion of the conductive layer that is adjacent to the plated through-hole and spaced from the bump, wherein the plated through-hole is in an electrically conductive path between the pad and the terminal;

providing a heat spreader that includes the bump, a base and a flange, wherein the bump is adjacent to the base and extends vertically from the base in the first vertical direction, the base covers the bump in the second vertical direction, extends laterally from the bump and includes a selected portion of the conductive layer that is spaced from the conductive trace and the flange includes a selected portion of the ledge that is adjacent to and integral with and extends laterally from the bump;

then

mounting a semiconductor device on the bump, wherein the semiconductor device extends into the cavity;

electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and

thermally connecting the semiconductor device to the bump, thereby thermally connecting the semiconductor device to the base.

107. The method of claim 106, wherein providing the bump includes mechanically stamping a metal plate, thereby forming the bump in the metal plate and the cavity in the bump, wherein the bump is a stamped portion of the metal plate and the ledge is an unstamped portion of the metal plate.

108. The method of claim 106, wherein:

providing the adhesive includes providing a prepreg with uncured epoxy;

flowing the adhesive includes melting the uncured epoxy and compressing the uncured epoxy between the ledge and the substrate; and

solidifying the adhesive includes curing the uncured epoxy.

109. The method of claim 106, wherein flowing the adhesive includes filling the gap with the adhesive.

110. The method of claim 106, wherein providing the pad and the flange includes removing selected portions of the ledge using an etch mask that defines the pad and the flange after forming the plated through-hole.

111. The method of claim 106, wherein providing the pad, the flange and the plated through-hole includes:

drilling a hole through the ledge, the dielectric layer, the adhesive and the conductive layer after solidifying the adhesive;

then

depositing a plated layer on the bump, the ledge, the dielectric layer, the adhesive and the conductive layer and into the hole, wherein the plated layer forms a first plated layer that covers the bump and the ledge in the first vertical direction and the plated through-hole in the hole;

then

forming an etch mask on the first plated layer that defines the pad and the flange;

etching the ledge and the first plated layer in a pattern defined by the etch mask; and

then

removing the etch mask.

112. The method of claim 106, wherein providing the base and the terminal includes removing selected portions of the conductive layer using an etch mask that defines the base and the terminal after forming the plated through-hole.

113. The method of claim 106, wherein providing the base and the terminal includes:

grinding the bump, the adhesive and the conductive layer such that the bump, the adhesive and the conductive layer are laterally aligned with one another at a lateral surface that faces in the second vertical direction; and

then

removing selected portions of the conductive layer using an etch mask that defines the base and the terminal.

114. The method of claim 106, wherein providing the base, the terminal and the plated through-hole includes:

drilling a hole through the ledge, the dielectric layer, the adhesive and the conductive layer after solidifying the adhesive;

then

depositing a plated layer on the ledge, the dielectric layer, the adhesive and the conductive layer and into the hole, wherein the plated layer forms a second plated layer that covers the bump, the adhesive and the conductive layer in the second vertical direction and the plated through-hole in the hole;

then

forming an etch mask on the second plated layer that defines the base and the terminal;

etching the conductive layer and the second plated layer in a pattern defined by the etch mask; and

then

removing the etch mask.

115. The method of claim 106, wherein mounting the semiconductor device includes providing a die attach between the semiconductor device and the bump, electrically connecting the semiconductor device includes providing a wire bond between the semiconductor device and the pad, and thermally connecting the semiconductor device includes providing the die attach between the semiconductor device and the bump.

116. A method of making a semiconductor chip assembly, comprising:

providing a bump and a ledge, wherein the bump defines a cavity that faces in a first vertical direction and has an entrance at the ledge, the bump is adjacent to and integral with the ledge and extends vertically from the ledge in a second vertical direction opposite the first vertical direction and the ledge extends laterally from the bump in lateral directions orthogonal to the vertical directions;

providing an adhesive, wherein an opening extends through the adhesive;

providing a substrate that includes a conductive layer and a dielectric layer, wherein an aperture extends through the substrate;

mounting the adhesive on the ledge, including inserting the bump into the opening, wherein the bump extends through the opening;

mounting the substrate on the adhesive, including inserting the bump into the aperture, wherein the bump extends into the aperture, the adhesive is sandwiched between the ledge and the dielectric layer and is non-solidified and the dielectric layer is sandwiched between the conductive layer and the adhesive;

then

applying heat to melt the adhesive;

moving the ledge and the substrate towards one another, thereby moving the bump in the second vertical direction in the aperture and applying pressure to the molten adhesive between the ledge and the substrate, wherein the pressure forces the molten adhesive to flow in the second vertical direction into a gap located in the aperture between the bump and the substrate;

applying heat to solidify the molten adhesive, thereby mechanically attaching the bump and the ledge to the substrate;

then

providing a plated through-hole that extends through the ledge, the adhesive, the dielectric layer and the conductive layer;

then

providing a pad, a terminal, a base and a flange;

providing a conductive trace that includes the pad, the terminal, the plated through-hole, a selected portion of the ledge that is adjacent to the plated through-hole and spaced from the bump and a selected portion of the conductive layer that is adjacent to the plated through-hole and spaced from the bump, wherein the plated through-hole is in an electrically conductive path between the pad and the terminal;

providing a heat spreader that includes the bump, the base and the flange, wherein the bump is adjacent to the base and extends vertically from the base in the first vertical direction, the base covers the bump in the second vertical direction, extends laterally from the bump in the lateral directions and includes a selected portion of the conductive layer that is spaced from the conductive trace and the flange includes a selected portion of the ledge that is adjacent to and integral with and extends laterally from the bump;

then

mounting a semiconductor device on the bump, wherein the semiconductor device extends into the cavity;

electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and

thermally connecting the semiconductor device to the bump, thereby thermally connecting the semiconductor device to the base.

117. The method of claim 116, wherein providing the bump includes mechanically stamping a metal plate, thereby forming the bump in the metal plate and the cavity in the bump, wherein the bump is a stamped portion of the metal plate and the ledge is an unstamped portion of the metal plate.

118. The method of claim 116, wherein:

providing the adhesive includes providing a prepreg with uncured epoxy;

flowing the adhesive includes melting the uncured epoxy and compressing the uncured epoxy between the ledge and the substrate; and

solidifying the adhesive includes curing the uncured epoxy.

119. The method of claim 116, wherein providing the base, the flange, the pad, the terminal and the plated through-hole includes:

drilling a hole through the ledge, the dielectric layer, the adhesive and the conductive layer after solidifying the adhesive;

then

depositing a plated layer on the bump, the ledge, the dielectric layer, the adhesive and the conductive layer and into the hole, wherein the plated layer forms a first plated layer that covers the bump and the ledge in the first vertical direction, a second plated layer that covers the bump, the adhesive and the conductive layer in the second vertical direction and the plated through-hole in the hole;

then

forming a first etch mask on the first plated layer that defines the pad and the flange;

etching the ledge and the first plated layer in a pattern defined by the first etch mask, thereby exposing the adhesive in the first vertical direction without exposing the dielectric layer in the first vertical direction;

forming a second etch mask on the second plated layer that defines the base and the terminal;

etching the conductive layer and the second plated layer in a pattern defined by the second etch mask, thereby exposing the dielectric layer in the second vertical direction without exposing the adhesive in the second vertical direction; and

removing the etch masks.

120. The method of claim 116, wherein mounting the semiconductor device includes providing a die attach between the semiconductor device and the bump, electrically connecting the semiconductor device includes providing a wire bond between the semiconductor device and the pad, and thermally connecting the semiconductor device includes providing the die attach between the semiconductor device and the bump.