Shielded gate trench MOSFET device and fabrication
First Claim
1. A method for fabricating a semiconductor device, comprising:
- forming a plurality of trenches, including applying a first mask;
forming a first polysilicon region in at least some of the plurality of trenches;
forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask;
forming a second polysilicon region in the at least some of the plurality of trenches;
forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask;
disposing a metal layer; and
forming a source metal region and a gate metal region, including applying a fourth mask.
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Accused Products
Abstract
A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.
64 Citations
21 Claims
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1. A method for fabricating a semiconductor device, comprising:
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forming a plurality of trenches, including applying a first mask; forming a first polysilicon region in at least some of the plurality of trenches; forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask; forming a second polysilicon region in the at least some of the plurality of trenches; forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask; disposing a metal layer; and forming a source metal region and a gate metal region, including applying a fourth mask. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification