Power MOSFET With Recessed Field Plate

• US 20110039384A1
• Filed: 10/27/2010
• Published: 02/17/2011
• Est. Priority Date: 09/27/2006
• Status: Abandoned Application

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Application Number:
  US12/912,811
• Publication Number:
  US 20110039384A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased.

Claims

1-19. -19. (canceled)

20. A method of fabricating a MOSFET comprising:

providing a semiconductor die;

etching the die so as to form a gate trench and a recessed field plate (RFP) trench, the gate trench and the RFP trench extending from a surface of the die and being of substantially equal depth;

forming an insulating layer at a bottom of the gate trench;

forming a gate dielectric layer on a sidewall of the gate trench above the insulating layer;

forming a second dielectric layer along the walls of the RFP trench;

introducing conductive material into the gate trench to form a gate electrode;

introducing conductive material into the RFP trench to form an RFP electrode;

implanting dopant of a first conductivity type form a body region in the mesa adjacent the sidewall of the gate trench;

implanting dopant of a second conductivity type opposite to the first conductivity type to form a source region in the mesa adjacent the surface of the die; and

depositing a source contact layer on the surface of the die in contact with the source region, the source contact layer comprising a conductive material.

21. The method of claim 20 comprising forming a third dielectric layer above the gate electrode such that the source contact layer is not in contact with the gate electrode.

22. The method of claim 21 wherein depositing a source contact layer causes the source contact layer to be in contact with the RFP electrode.

23. The method of claim 22 comprising implanting dopant of a first conductivity type to form a body contact region adjacent the body region and a sidewall of the RFP trench, the method further comprising etching the RFP electrode into the RFP trench such that depositing a source contact layer causes the source contact layer to be in contact with the body contact region.

24. The method of claim 20 comprising:

forming a mask layer on the surface of the die;

patterning the mask layer to form three openings, a first opening being located where the RFP trench is to be formed, a second opening being located where the gate trench is to be located, and a third opening being located where a second RFP trench is to be located, the second opening being located between and equidistant from the first and third openings; and

wherein etching the die comprises etching the die through the first, second and third openings to form the RFP trench, the gate trench and the second RFP trench, respectively, the gate trench being located between and equidistant from the RFP and second RFP trenches.

25. The method of claim 24 wherein etching the die causes the gate trench and the RFP trenches to have respective depths within a tolerance of +/−

10%.