FLASH-based Memory System With Variable Length Page Stripes Including Data Protection Information

• US 20110040926A1
• Filed: 09/05/2009
• Published: 02/17/2011
• Est. Priority Date: 08/11/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: Texas Memory Systems Incorporated (International Business Machines Corporation)
• Inventors: Frost, Holloway H., Camp, Charles J., Fuxa, James A.
• Granted Patent: US 8,176,284 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using different size page stripes. The controller is configured to store data in FLASH memory devices in the form of page stripes, each page stripe comprising a plurality of pages of information, each page of information being stored in a different FLASH memory chip. The controller stores the data in a manner such that the pages making up each page stripe includes a plurality of data pages and at least one data protection page. In one implementation, the page stripes stored by the controller include a first page stripe having N data pages and one data protection page, and a second page stripe having M data pages and one data protection page, where N is an integer greater than three and M is an integer less than N.

Claims

1. A FLASH memory based solid state storage system comprising:

(a) a printed circuit board;

(b) a fixed number of FLASH memory chips mounted to the printed circuit board, each FLASH memory chip having the same physical construction and including a plurality of FLASH memory cells arranged to store a plurality of pages of digital data and a chip-level communications bus interface capable of receiving and sending digital data to be stored in, and retrieved from, FLASH memory cells within the FLASH memory chip; and

(c) a system controller mounted to the printed circuit board, the system controller including a plurality of system communication bus interfaces, each system communication bus interface being coupled by a system communications bus to one or more chip-level communication bus interfaces such that the system controller can provide digital data to and retrieve digital data from memory cells within the one or more FLASH memory chips, the system controller further including an external communications bus interface capable of receiving digital data to be stored within the storage system;

(d) wherein the system controller is configured to store data received over the external communications bus in the plurality of FLASH memory chips in the form of page stripes, each page stripe comprising a plurality of pages of information stored in physical memory locations within the FLASH memory chips, each of the plurality of pages of information being stored in a FLASH memory chip that is different from each of the FLASH memory chips in which the other pages of information within the page stripe are stored, the plurality of pages making up each page stripe including;

(i) a plurality of data pages, and

(ii) at least one data protection page containing data protection information that may be used to reconstruct data stored in a data page within the page stripe that becomes corrupted or unavailable, the data protection information for a given page stripe being obtained by performing a logical operation on the information within the data pages for the given page stripe; and

(e) wherein the system controller is further configured to create page stripes using information associated with physical memory locations previously used to store information that are available for the storage of different information such that at least some of the created page stripes stored by the system controller include;

(i) a first page stripe stored within the plurality of FLASH memory chips, the first page stripe having N data pages and one data protection page, where N is an integer greater than three and equal to one less than the number of FLASH memory chips; and

(ii) a second page stripe stored within the plurality of FLASH memory chips, the second page stripe having M data pages and one data protection page, where M is an integer less than N and wherein the second page stripe includes a physical memory location previously included in a page stripe having N data pages.

2. The FLASH memory based solid state storage system of claim 1 wherein each of the data pages within the second page stripe is stored within a FLASH memory chip that also stores data from a data page within the first data stripe.

3. The FLASH memory based solid state storage system of claim 1 wherein the logical operation used to obtain the data protection information for each page stripe is the bitwise exclusive-or (XOR) operation.

4. The FLASH memory based solid state storage system of claim 3 further comprising circuitry for generating the data protection information for each page stripe by performing XOR operations on data from the data pages within the page stripe.

5. The FLASH memory based solid state storage system of claim 1 wherein N is nine.

6. The FLASH memory based solid state storage system of claim 1 wherein the system controller is configured such that each data page includes error correction code data, the error correction code data being generated by the system controller using data within the page that was initially received over the external communication bus.

7. The FLASH memory based solid state storage system of claim 6 wherein the system controller is configured to use the error correction code data within each data page to identify information within a given page that is corrupted or unavailable.

8. A board-mounted FLASH-based memory storage system comprising:

(i) a printed circuit board;

(ii) a plurality of FLASH memory devices, each mounted to the printed circuit board;

(iii) a controller mounted to the printed circuit board; and

(iv) a plurality of communications buses, each configured to allow the controller to write a data collection to one or more FLASH memory devices;

(v) wherein the controller is configured to write data to the FLASH memory devices in a striped fashion using data stripes, where each data stripe includes a group of data collections and an associated set of data protection information such that;

(a) each data collection within a group of data collections is written into a FLASH memory device that differs from (1) the FLASH memory devices into which the other data collections within the group of data collections are written and (2) the FLASH memory device to which the data protection information associated with the group of data collections is written;

(b) each data collection includes error correction code data generated from the data stored in the data collection; and

(c) each set of data protection information is generated by performing a bitwise exclusive-or (XOR) of the data within the data collections associated with the set of data protection information;

(vi) wherein the controller is adapted to use the error correction code data within each data collection to identify an error within the data collection;

(vii) wherein the controller further includes circuitry for using the set of data protection information to reconstruct the data for a data collection associated with the set of data protection information; and

(viii) wherein the controller is configured to;

(a) maintain a listing of physical storage locations within the FLASH memory devices that previously stored data and are ready to be erased such that they are available for storing data, (b) use the listing of physical storage locations to group physical storage locations together to store data for a group of data collections and (c) vary the number of physical storage locations that are grouped together such that (i) the number of data collections within the group of data collections is variable;

(ii) groups of data collections having differing numbers of data collections are stored in a plurality of the FLASH memory devices; and

(iii) a physical memory location previously associated with a group of data collections having a first number of data collections is associated with a group of data collections having a second, different, number of data collections.

9. The board-mounted FLASH-based memory storage system of claim 8 where the number of bits in each data collection is equal to the number of bits in each set of data protection information.

10. The board-mounted FLASH-based memory storage system of claim 8 wherein the controller is a field programmable gate array including circuitry for calculating the bitwise XOR of a plurality of data collections within a group of data collections.

11. The board-mounted FLASH-based memory storage system of claim 8 further including a first group of M data collections stored in the plurality of FLASH memory devices and a second group of N data collections stored in the plurality of FLASH memory devices, where M is an integer number greater than three and where N is less than M.

12. The board-mounted FLASH memory storage system of claim 11 wherein there are O FLASH memory devices, where O is an integer greater than M.

13. The board-mounted FLASH-based memory storage system of claim 12 wherein the number of communications buses is equal to O divided by two.

14. The board-mounted FLASH-based memory storage system of claim 8 wherein each of the plurality of FLASH memory devices is a FLASH memory chip, and wherein each FLASH memory chip is surface mounted to the printed circuit board.

15. A memory system comprising:

M+1 FLASH memory chips, where M is an integer greater than three;

a system controller coupled to the FLASH memory chips, wherein the system controller writes information to the FLASH memory chips using data stripes;

a first data stripe stored in the M+1 FLASH memory chips, the first data stripe including M data pages and a data protection page, wherein information stored in the data protection page for the first data stripe was generated through the performance of a given operation on information stored within the M data pages of the first data stripe; and

a second data stripe stored in N+1 of the M+1 FLASH memory chips, the second data stripe including N data pages and a data protection page, where N is an integer less than M, and wherein information stored in the data protection page for the second data stripe was generated from the performance of the given operation on information stored within the N data pages of the second stripe and wherein one of the memory locations within the FLASH memory chips used to store the second data stripe was previously used to store data from a data stripe having M data pages.

16. The memory system of claim 15 wherein the given operation is a bitwise exclusive-or (XOR) operation.

17. The memory system of claim 15 wherein each data page within the first data stripe is stored in a FLASH chip that is different from the FLASH chips in which the other data pages within the first data stripe are stored.

18. The memory system of claim 17 wherein each data page within the second data stripe is stored in a FLASH memory chip that is different from the FLASH memory chips in which the data pages within the second data stripe are stored.

19. The memory system of claim 15 wherein the number of bits of information stored in each data page of the first data stripe is the same and wherein the number of bits of information stored in each data page of the second data stripe is the same as the number of bits of information stored in each data page of the first data stripe.

20. The memory system of claim 19 wherein the number of bits of information stored in the data protection page for the first data stripe is the same as the number of bits of information stored in the data protection page for the second data stripe.