Method and Apparatus for Performing Enhanced Read and Write Operations in a FLASH Memory System
First Claim
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1. A FLASH-based solid state storage system comprising:
- a system controller including an external communication bus interface adapted to receive WRITE requests from an external host, where each WRITE request includes a Logical Block Address (LBA) and a page of data to be stored at the LBA;
a volatile memory space accessible to the system controller;
a FLASH memory space containing a plurality of physical address locations, each physical address location being capable of storing a page of data; and
one or more communication buses coupling the system controller to the FLASH memory space,wherein the system controller is configured to maintain a logical to physical translation table in the volatile memory space, where the logical to physical translation table includes both;
(i) entries associating a LBA with a physical address location within the FLASH memory space where, for each such entry, data is stored within the physical address location within the FLASH memory space; and
(ii) entries associating a LBA with one or more data identifiers, where;
(a) each such data identifier is associated with a specific data string,(b) each such data string corresponds to a specific block of data and not to any physical address location within the FLASH memory space; and
(c) no physical address location within the FLASH memory space includes stored data corresponding to any of the specific blocks of data that correspond to a data string.
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Abstract
Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.
75 Citations
20 Claims
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1. A FLASH-based solid state storage system comprising:
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a system controller including an external communication bus interface adapted to receive WRITE requests from an external host, where each WRITE request includes a Logical Block Address (LBA) and a page of data to be stored at the LBA; a volatile memory space accessible to the system controller; a FLASH memory space containing a plurality of physical address locations, each physical address location being capable of storing a page of data; and one or more communication buses coupling the system controller to the FLASH memory space, wherein the system controller is configured to maintain a logical to physical translation table in the volatile memory space, where the logical to physical translation table includes both; (i) entries associating a LBA with a physical address location within the FLASH memory space where, for each such entry, data is stored within the physical address location within the FLASH memory space; and (ii) entries associating a LBA with one or more data identifiers, where; (a) each such data identifier is associated with a specific data string, (b) each such data string corresponds to a specific block of data and not to any physical address location within the FLASH memory space; and (c) no physical address location within the FLASH memory space includes stored data corresponding to any of the specific blocks of data that correspond to a data string. - View Dependent Claims (2, 3, 4, 5, 6, 8)
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7. (canceled)
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9. A method for limiting the number of operations performed on a FLASH memory and of preventing the writing of certain blocks of data into the FLASH memory, the method comprising the steps of:
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receiving a WRITE request including an identification of a logical block address and a block of data corresponding to the block address; determining whether the received block of data provided in the WRITE request corresponds to a predefined block of data; and if the determination step indicates that the received block of data corresponds to the predefined block of data;
associating the received logical block address with a data identifier, the data identifier providing a representation of the predefined block of data and not writing the predefined block of data to a physical address in the FLASH memory, such that no blocks of data stored within the FLASH memory correspond to the predefined block of data;
orif the determination step indicates that the received block of data does not correspond to the predefined block of data;
associating the received logical block address with a physical address in the FLASH memory and writing the received block of data to the physical address in the FLASH memory. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A memory system for storing data in one or more FLASH memory devices, the memory system comprising:
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a system controller adapted to receive WRITE requests, each write request including a logical address identifier and a set of data; and a logical to physical translation table accessible to the system controller and stored in volatile RAM memory, the logical to physical translation table including at least; a first entry associating a first logical address with a physical address in a FLASH memory space; a second entry associating a second logical address with a data identifier, where the second logical address is different from the first logical address and wherein the data identifier represents a predefined set of data wherein the predefined set of data is not stored within any physical address in the FLASH memory space; and a third entry associating a third logical address with the data identifier, wherein the third logical address is different from the first and second logical addresses. - View Dependent Claims (16, 17, 18, 19)
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20. (canceled)
Specification