APPARATUS AND METHODS FOR ELECTROCHEMICAL PROCESSING OF MICROFEATURE WAFERS

• US 20110042224A1
• Filed: 11/02/2010
• Published: 02/24/2011
• Est. Priority Date: 01/29/2007
• Status: Active Grant

• Current Assignee: Semitool Incorporated (Applied Materials Incorporated)
• Original Assignee: Semitool Incorporated (Applied Materials Incorporated)
• Inventors: McHugh, Paul R., Woodruff, Daniel J., Wilson, Gregory J.
• Granted Patent: US 8,313,631 B2
• Time in Patent Office: Days
• US Class Current: 205/123
• CPC Class Codes: C25D 17/001 Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
• CPC Class Codes: C25D 17/10 Electrodes , e.g. composition, counter electrode
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: C25F 3/30 of semiconducting materials

Abstract

Apparatus and methods for electrochemically processing microfeature wafers. The apparatus can have a vessel including a processing zone in which a microfeature wafer is positioned for electrochemical processing. The apparatus further includes at least one counter electrode in the vessel that can operate as an anode or a cathode depending upon the particular plating or electropolishing application. The apparatus further includes a supplementary electrode and a supplementary virtual electrode. The supplementary electrode is configured to operate independently from the counter electrode in the vessel, and it can be a thief electrode and/or a de-plating electrode depending upon the type of process. The supplementary electrode can further be used as another counter electrode during a portion of a plating cycle or polishing cycle. The supplementary virtual electrode is located in the processing zone, and it is configured to counteract an electric field offset relative to the wafer associated with an offset between the wafer and the counter electrode in the vessel when the wafer is in the processing zone.

Claims

1. A method for electrochemically processing a microfeature wafer, comprising:

holding a wafer in a wafer holder in a processing zone of a vessel;

establishing an electric field in a processing fluid in the vessel using the wafer, a counter electrode in the vessel, and a supplementary electrode spaced apart from the wafer holder; and

counteracting an offset of the electric field relative to the wafer associated with an offset between the wafer holder and the vessel.

2. The method of claim 1 wherein the supplementary electrode affects the electric field via a supplementary virtual electrode in the processing zone, and wherein counteracting for the offset of the electric field relative to the wafer comprises shaping the supplementary virtual electrode to have a first width at a first side of the wafer holder and a second width different than the first width at a second side of the wafer holder.

4. The method of claim 1 further comprising separating controlling a first electrical current supply to the supplementary electrode and a second electrical current supply to the counter electrode.

7. The method of claim 1 wherein the supplementary electrode is located above the processing zone, and further comprising plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

8. The method of claim 1 wherein the supplementary electrode is located above the counter electrode, and further comprising de-plating material using the supplementary electrode.

9. The method of claim 1 wherein the supplementary electrode is located above the processing zone, and further comprising de-plating material using the supplementary electrode.

10. The method of claim 1 wherein the vessel includes a member having an inner edge, a rim above the inner edge, and a perimeter, and wherein the supplementary electrode is located above the member at a radial position between the inner edge and the perimeter, and further comprising plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

11. The method of claim 10 further comprising shaping an electric field component using a supplementary virtual electrode having an aperture formed, at least in part, by the inner edge of the member, and further comprising plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

12. The method of claim 10 further comprising shaping an electric field component using a supplementary virtual electrode has an aperture formed, at least in part, by the inner edge of the member, and further comprising plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

13. The method of claim 10 further comprising establishing the electric field using a plurality of counter electrodes and operating the counter electrodes independently from each other and the supplementary electrode.

14. The method of claim 10 wherein counteracting the offset comprises configuring at least one of an inner edge of the vessel and an outer surface of the wafer holder to have a shape that defines a supplementary virtual electrode that compensates for the offset.

15. The method of claim 14 further comprising changing a shape of at least one of the inner edge of the vessel or the outer surface of the wafer holder.

16. The method of claim 14 further comprising replacing the inner edge or the wafer holder with a different inner edge or wafer holder.

17. The method of claim 1 further comprising operating a plurality of counter electrodes independently from each other and the supplementary electrode.

3. The method of 1 wherein the supplementary electrode affects the electric field via a supplementary virtual electrode defined, at least in part, by a portion of the vessel at the processing zone and a portion of the wafer holder.

5. The method of claim 3 wherein the supplementary electrode affects the electric field via a supplementary virtual electrode in the processing zone, and wherein counteracting for the offset of the electric field relative to the wafer comprises shaping the supplementary virtual electrode to have a first width at a first side of the wafer holder and a second width different than the first width at a second side of the wafer holder.

6. The method of 1 wherein the supplementary electrode is located above the counter electrode, and further comprising plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

18. A method for electrochemically processing a microfeature wafer, comprising:

flowing a processing fluid upwardly through a processing zone in a vessel;

flowing the processing fluid over a rim over of the processing vessel and out of the processing zone;

holding a wafer in a wafer holder in the processing fluid in the processing zone;

applying electrical current to the wafer;

applying electrical current to at least one counter electrode in the vessel;

applying electrical current to a supplementary electrode spaced apart from the wafer; and

applying current to a virtual supplementary electrode having an aperture configured to shape an electric field component from the supplementary electrode, and shaping the aperture, at least in part, by alignment between the wafer holder and the vessel to counteract non-uniformities associated with an offset between the wafer holder and the vessel.

19. The method of claim 18 further comprising applying electrical current to a plurality of counter electrodes operating independently from each other and the supplementary electrode.