STRUCTURES OF AND METHODS OF FABRICATING TRENCH-GATED MIS DEVICES
First Claim
1. A trench-gated MIS device in a semiconductor chip and comprising:
- a first active area containing transistor cells;
a second active area containing transistor cells;
a gate metal area containing no transistor cells, wherein the first and second active areas are located on opposite sides of the gate metal area; and
a gate metal layer overlying the gate metal area,wherein a first plurality of trenches are formed in a pattern on a surface of the semiconductor chip, the first plurality of trenches extending from the first active area into the gate metal area, a second plurality of trenches are formed in the pattern on the surface of the semiconductor chip, the second plurality of trenches extending from the second active area into the gate metal area, the first plurality and second plurality of trenches having walls lined with a layer of an insulating material, a conductive gate material being disposed in the trenches, a top surface of the conductive gate material being at a level below a top surface of the semiconductor chip, a nonconductive layer overlying the active and gate metal areas, and the gate metal layer overlying the nonconductive layer in the gate metal area.
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Accused Products
Abstract
In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
78 Citations
20 Claims
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1. A trench-gated MIS device in a semiconductor chip and comprising:
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a first active area containing transistor cells; a second active area containing transistor cells; a gate metal area containing no transistor cells, wherein the first and second active areas are located on opposite sides of the gate metal area; and a gate metal layer overlying the gate metal area, wherein a first plurality of trenches are formed in a pattern on a surface of the semiconductor chip, the first plurality of trenches extending from the first active area into the gate metal area, a second plurality of trenches are formed in the pattern on the surface of the semiconductor chip, the second plurality of trenches extending from the second active area into the gate metal area, the first plurality and second plurality of trenches having walls lined with a layer of an insulating material, a conductive gate material being disposed in the trenches, a top surface of the conductive gate material being at a level below a top surface of the semiconductor chip, a nonconductive layer overlying the active and gate metal areas, and the gate metal layer overlying the nonconductive layer in the gate metal area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A trench-gated MIS device in a semiconductor chip and comprising:
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a first active area containing transistor cells; a second active area containing transistor cells; a gate metal area containing no transistor cells, wherein the first and second active areas are located on opposite sides of the gate metal area; and a gate metal layer overlying the gate metal area, wherein a first plurality of trenches are formed in a pattern on a surface of the semiconductor chip, the first plurality of trenches extending from the first active area into the gate metal area, a second plurality of trenches are formed in the pattern on the surface of the semiconductor chip, the second plurality of trenches extending from the second active area into the gate metal area. - View Dependent Claims (17)
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18. A trench-gated MIS device in a semiconductor chip and comprising:
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a first active area containing transistor cells; a second active area containing transistor cells; a gate metal area containing no transistor cells, wherein the first and second active areas are located on opposite sides of the gate metal area; a gate metal layer overlying the gate metal area; a first plurality of trenches extending from the first active area into the gate metal area; and a second plurality of trenches extending from the second active area into the gate metal area. - View Dependent Claims (19, 20)
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Specification