MEMORY DEVICE COMPRISING AN ARRAY PORTION AND A LOGIC PORTION

• US 20110042755A1
• Filed: 11/05/2010
• Published: 02/24/2011
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 8,207,583 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

Claims

1. A memory device comprising:

a substrate having an array portion and a logic portion;

a plurality of semiconductor structures that are recessed in the array portion of the substrate;

a plurality of transistor devices formed over the logic portion of the substrate, wherein the transistor devices include a gate oxide layer, an uncapped gate layer, and a sidewall spacer structure, and wherein the transistor devices are formed in a layer that is below the plurality of semiconductor structures.

2. The memory device of claim 1, wherein each of the plurality of semiconductor devices occupies an area of the substrate array portion between about 4F² and about 8F², wherein F is the minimum resolvable feature size formable using a photolithographic technique that is used to define features of the semiconductor structures.

3. The memory device of claim 2, wherein each of the plurality of semiconductor devices occupies an area of the substrate having a length dimension that is not equal to a width dimension.

4. The memory device of claim 2, wherein each of the plurality of semiconductor devices occupies an area of the substrate having a length dimension that is equal to a width dimension.

5. The memory device of claim 1, wherein the plurality of semiconductor devices form a pattern having a first pitch, and wherein the plurality of transistor devices form a pattern having a second pitch that is at least two times the first pitch.

6. The memory device of claim 1, wherein the plurality of transistor devices are formed using a photolithographic mask that is also simultaneously used to pattern at least a portion of the plurality of semiconductor structures recessed in the array portion of the substrate.

7. The memory device of claim 1, wherein the plurality of semiconductor structures are defined by a pattern of alternating deep and shallow trenches that are crossed by a pattern of intermediate-depth trenches.

8. The memory device of claim 7, wherein the alternating deep and shallow trenches are filled with an oxide material.

9. The memory device of claim 7, wherein the alternating deep and shallow trenches are filled with a spin-on dielectric material.

10. The memory device of claim 7, wherein the shallow trenches are at least partially filled with a semiconductor material.

11. The memory device of claim 1, wherein the semiconductor structures include a channel portion that is contiguous with the substrate array portion.

12. The memory device of claim 1, wherein the substrate comprises single crystal silicon.

13. The memory device of claim 1, wherein the plurality of transistor devices formed over the logic portion of the substrate are planar transistor devices.

14. The memory device of claim 1, wherein the plurality of transistor devices formed over the logic portion of the substrate include a silicide region positioned over the uncapped gate layer.

15. The memory device of claim 14, wherein the silicide region comprises a material selected from the group consisting of tungsten silicide and titanium silicide.

16. A partially-formed integrated circuit comprising:

a first plurality of features comprising a first material and formed over a first portion of a substrate, wherein the first plurality of features are separated from each other by a first spacing;

a second plurality of features comprising a second material and formed over a second portion of the substrate, wherein the first plurality of features and the second plurality of features are formed simultaneously, and wherein the first material is the same as the second material;

a gap fill structure positioned between and contacting a selected two of the first plurality of features; and

a plurality of sidewall spacers positioned adjacent the second plurality of features, wherein adjacent sidewall spacers are separated from each other by a separation region, and wherein the plurality of sidewall spacers and the gap fill structure comprise the same material.

17. The partially-formed integrated circuit of claim 16, wherein the first portion of the substrate comprises:

a plurality of elongate shallow trenches;

a plurality of elongate deep trenches positioned substantially parallel to the plurality of elongate shallow trenches; and

a plurality of elongate silicon regions that separate the plurality of elongate shallow trenches and the plurality of elongate deep trenches.

18. The partially-formed integrated circuit of claim 17, wherein the first and second plurality of features comprise elongate polycrystalline silicon features that cross the plurality of elongate shallow trenches.

19. The partially-formed integrated circuit of claim 16, wherein the first and second plurality of features comprise elongate gate stacks.

20. The partially-formed integrated circuit of claim 16, wherein:

the first plurality of features form a pattern of sacrificial material; and

the second plurality of features forms part of a plurality of final structures positioned over the second portion of the substrate.

21. The partially-formed integrated circuit of claim 20, wherein the plurality of final structures are planar transistors.

22. The partially-formed integrated circuit of claim 16, wherein the gap fill structure forms a portion of a hard mask pattern.

23. The partially-formed integrated circuit of claim 22, wherein the hard mask pattern defines trenches for a U-shaped transistor structure.