UNINTERRUPTIBLE POWER SUPPLY

• US 20110043042A1
• Filed: 10/29/2010
• Published: 02/24/2011
• Est. Priority Date: 08/15/2003
• Status: Active Grant

• Current Assignee: American Power Conversion Corporation (Schneider Electric SE)
• Original Assignee: American Power Conversion Corporation (Schneider Electric SE)
• Inventors: SAMSTAD, JEFFREY B., KLIKIC, DAMIR, KOTLYAR, EDWARD, BEG, MIRZA A., MELANSON, MARK R.
• Granted Patent: US 8,134,811 B2
• Time in Patent Office: Days
• US Class Current: 307/66
• CPC Class Codes: H02J 9/062 for AC powered loads
• CPC Class Codes: H02M 1/10 Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from ac or dc

Abstract

An uninterruptible power supply (UPS) system includes an AC power input configured to receive AC power from a single-phase AC power source or a multi-phase AC power source, a DC power source, an output circuit including a power output, a controllable switch configured to selectively couple at least one of the AC power input and the DC power source to the output circuit, and a processor coupled and configured to affect operation of the output circuit depending upon which of single-phase and multi-phase operation of the UPS is indicated.

Claims

1-8. -8. (canceled)

9. A circuit for selectively coupling a battery to a load, the circuit comprising:

an input for receiving power from the battery;

an output for providing power from the circuit to the load;

an isolation switch;

a resistance coupled to the isolation switch and the output; and

a bypass switch coupled to the input and the output and configured to selectively couple the input to the output while bypassing the isolation switch and the resistance;

wherein the isolation switch is configured to selectively couple the input to the resistance.

10. The circuit of claim 9 wherein the isolation switch is coupled to receive a signal indicating whether a logic power supply associated with the circuit is on, and to couple the input to the resistance if the logic power supply is on.

47. The circuit of claim 9, further comprising a processor coupled to the output, wherein the processor is configured provide a signal to control an operation of the bypass switch.

48. The circuit of claim 47, further comprising a capacitor coupled to the output.

49. The circuit of claim 48, wherein the processor is configured to provide a signal to open the bypass switch during a charging period of the capacitor, and

wherein the processor is configured to provide a signal to close the bypass switch once the capacitor is charged.

50. The circuit of claim 49, wherein the signal includes a relay control signal.

51. The circuit of claim 49 wherein the isolation switch is coupled to receive a signal indicating whether a logic power supply associated with the circuit is on, and to couple the input to the resistance if the signal indicates that the logic power supply is on.

52. The circuit of claim 51, wherein the processor operates from power provided by the logic power supply.

11-46. -46. (canceled)

53. An uninterruptible power supply (UPS) system comprising:

a DC power source;

a processor configured to monitor the DC power source;

a resistor coupled to the processor;

a logic power supply configured to supply power to the processor;

a first switch configured to couple the DC power source to the processor via the resistor when the logic power supply is active and to isolate the DC power source from the processor when the power supply is inactive; and

a second switch that when closed is configured to couple the DC power source to the processor and bypass the resistor.

54. The UPS of claim 53, wherein the DC power source includes batteries.

55. The UPS of claim 53, further comprising a capacitor coupled to the resistor and the processor.

56. The UPS of claim 55, wherein the processor is configured to control an operation of the second switch to control a flow of current during a startup period.

57. The UPS of claim 56, wherein the processor is configured to provide a first signal to open the second switch during a charging period of the capacitor, and

wherein the processor is configured to provide a second signal to close the second switch once the capacitor is charged.

58. The UPS of claim 57, wherein the processor is configured to provide the second signal to close the switch to control a flow of current

59. The UPS of claim 58, wherein the second switch is included in a relay, and

wherein the first signal and the second signal are relay control signals.