METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE

• US 20110043248A1
• Filed: 10/29/2010
• Published: 02/24/2011
• Est. Priority Date: 09/04/1996
• Status: Active Grant

• Current Assignee: Benjamin S. Ting, Peter M. Pani
• Original Assignee: Benjamin S. Ting, Peter M. Pani
• Inventors: Ting, Benjamin S., Pani, Peter M.
• Granted Patent: US 7,915,918 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.

Claims

1. A programmable integrated circuit device, comprising:

first and second megacells of a first plurality of megacells, each of the first and second megacells having a plurality of input/output ports;

a first line of a first plurality of lines, wherein;

the first plurality of lines comprises a bus associated with the first plurality of megacells,

the first line is programmably coupleable to a first input/output port of the first megacell, and

the first line is programmably coupleable to a second input/output port of the second megacell; and

a first programmable combinatorial logic element programmably coupleable to the first line.

2. The programmable integrated circuit device of claim 1, further comprising:

third and fourth megacells of a second plurality of megacells, each of the third and fourth megacells having a plurality of input/output ports;

a second line of a second plurality of lines, wherein;

the second plurality of lines comprises a bus associated with the second plurality of megacells,

the second line is programmably coupleable to a third input/output port of the third megacell, and

the second line is programmably coupleable to a fourth input/output port of the fourth megacell; and

a second programmable combinatorial logic element programmably coupleable to the second line.

3. The programmable integrated circuit device of claim 2, wherein the first line is programmably coupleable to the second line.

4. The programmable integrated circuit device of claim 3, wherein:

the first plurality of lines is a core bus; and

the second plurality of lines is a core bus.

5. The programmable integrated circuit device of claim 3, wherein:

the first plurality of lines is a core bus; and

the second plurality of lines is a peripheral bus.

6. The programmable integrated circuit device of claim 1, further comprising:

a third input/output port of the first megacell;

a fourth input/output port of the second megacell;

a second programmable combinatorial logic element; and

a second line of the first plurality of lines, wherein;

the third input/output port is programmably coupleable to the second line,

the fourth input/output port is programmably coupleable to the second line, and

the second programmable combinatorial logic element is programmably coupleable to the second line.

7. The programmable integrated circuit device of claim 6, wherein:

the first plurality of lines is a peripheral bus;

the first and second input/output ports are outputs; and

the third and fourth input/output ports are inputs.

8. The programmable integrated circuit device of claim 6, wherein:

the first plurality of lines is a core bus;

the first and second input/output ports are outputs; and

the third and fourth input/output ports are inputs.

9. The programmable integrated circuit device of claim 6, wherein the first line and second lines are bidirectional.

10. The programmable integrated circuit device of claim 1, wherein the first plurality of lines is a peripheral bus.

11. The programmable integrated circuit device of claim 1, wherein the first plurality of lines is a core bus.

12. The programmable integrated circuit device of claim 1, wherein the first input/output port is an output.

13. The programmable integrated circuit device of claim 1, wherein the first input/output port is an input.

14. The programmable integrated circuit device of claim 1, further comprising:

a second line of a second plurality of lines, wherein the first line of the first plurality of lines is programmably coupleable to the second line of the second plurality of lines; and

a first input/output pad coupled to the second line of the second plurality of lines.

15. The programmable integrated circuit device of claim 14, wherein the first input/output pad is coupled to the second line of the second plurality of lines through a programmable connection.

16. The programmable integrated circuit device of claim 14, wherein the first line of the first plurality of lines is programmably coupleable to the second line of the second plurality of lines through a three-statable connection.

17. The programmable integrated circuit device of claim 14, wherein the first input/output pad is coupled to the second line of the second plurality of lines through a direct hardwired connection.

18. The programmable integrated circuit device of claim 14, wherein:

the first plurality of lines is a peripheral bus; and

the second plurality of lines comprises I-matrix lines.

19. The programmable integrated circuit device of claim 14, wherein the first and second lines are bidirectional.

20. The programmable integrated circuit device of claim 1, wherein the first line is bidirectional.

21. A programmable integrated circuit device, comprising:

a first plurality of lines comprising a bus associated with a first plurality of megacells;

a first megacell of the plurality of megacells having a first plurality of input/output ports, wherein;

each input/output port of the first plurality of input/output ports is programmably coupleable to at least one line of the first plurality of lines, and

each line of the first plurality of lines is programmably coupleable to at least one of the input/output ports of the first plurality of input/output ports; and

a programmable combinatorial logic element programmably coupleable to a first line of the first plurality of lines.

22. The programmable integrated circuit device of claim 21, wherein the first plurality of lines is a peripheral bus.

23. The programmable integrated circuit device of claim 21, wherein the first plurality of lines is a core bus.

24. The programmable integrated circuit device of claim 21, further comprising:

a second line of a second plurality of lines programmably coupleable to the programmable combinatorial logic element;

an input/output pad coupled to the second line of the second plurality of lines.

25. The programmable integrated circuit device of claim 24, wherein the input/output pad is coupled to the second line of the second plurality of lines through a direct hardwired connection.

26. The programmable integrated circuit device of claim 24, wherein the first input/output pad is coupled to the second line of the second plurality of lines through a programmable connection.

27. The programmable integrated circuit device of claim 26, wherein:

the first plurality of lines is a peripheral bus; and

the second plurality of lines comprises I-matrix lines.

28. The programmable integrated circuit device of claim 24, wherein:

the first plurality of lines is a peripheral bus; and

the second plurality of lines comprises I-matrix lines.

29. The programmable integrated circuit device of claim 24, further comprising a second megacell of the plurality of megacells having a second plurality of input/output ports, wherein:

each input/output port of the first plurality of input/output ports is programmably coupleable to at least one line of the first plurality of lines, and

each line of the first plurality of lines is programmably coupleable to at least one of the input/output ports.

30. The programmable integrated circuit device of claim 29, wherein the first plurality of lines is a core bus.

31. The programmable integrated circuit device of claim 21, further comprising a second megacell of the plurality of megacells having a second plurality of input/output ports, wherein:

each input/output port of the first plurality of input/output ports is programmably coupleable to at least one line of the first plurality of lines, and

each line of the first plurality of lines is programmably coupleable to at least one of the input/output ports.

32. The programmable integrated circuit device of claim 31, wherein the first plurality of lines is a core bus.

33. The programmable integrated circuit device of claim 24, further comprising:

a third plurality of lines comprising a bus associated with the first plurality of megacells; and

a second plurality of input/output ports of the first megacell, wherein;

each input/output port of the second plurality of input/output ports is programmably coupleable to at least one line of the third plurality of lines, and

each line of the third plurality of lines is programmably coupleable to at least one of the input/output ports of the second plurality of input ports.

34. The programmable integrated circuit device of claim 21, further comprising:

a second plurality of lines comprising a bus associated with the first plurality of megacells; and

a second plurality of input/output ports of the first megacell, wherein;

each input/output port of the second plurality of input/output ports is programmably coupleable to at least one line of the second plurality of lines, and

each line of the second plurality of lines is programmably coupleable to at least one of the input/output ports of the second plurality of input ports.