Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

• US 20110043271A1
• Filed: 06/18/2010
• Published: 02/24/2011
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Bawell, Shawn, Englekirk, Robert Mark, Greene, Robert W., Brindle, Christopher N., Ranta, Tero Tapio
• Granted Patent: US 8,638,159 B2
• Time in Patent Office: Days
• US Class Current: 327/427
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01G 4/002 Details
• CPC Class Codes: H01G 7/00 Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H03H 11/28 Impedance matching networks
• CPC Class Codes: H03H 7/0153 Electrical filters; Controlling thereof
• CPC Class Codes: H03H 7/38 Impedance-matching networks
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Claims

1. A unit cell for a sub-circuit of a digitally tunable capacitor (DTC), the sub-circuit being adapted to be coupled between a first RF terminal and a second RF terminal, the unit cell comprising:

a plurality of stacked switches coupled in series with one or more capacitors, the stacked switches proceeding from a first switch closest the first RF terminal and farthest from the second RF terminal to an n-th switch farthest from the first RF terminal and closest to the second RF terminal,

wherein the one or more capacitors are placed symmetrically with respect to the plurality of stacked switches.

2. The unit cell of claim 1, wherein the one or more capacitors are metal-insulator-metal (MIM) capacitors or metal-metal (MM) capacitors.

3. The unit cell of claim 1, wherein the one or more capacitors are placed in a middle of a stack formed by the plurality of stacked switches.

4. The unit cell of claim 2, wherein the one or more capacitors are placed in a middle of a stack formed by the plurality of stacked switches.

5. The unit cell of claim 1, wherein the one or more capacitors are a first set of one or more capacitors placed between the first RF terminal and the first switch and a corresponding set of one or more capacitors placed between the n-th switch and the second RF terminal.

6. The unit cell of claim 2, wherein the one or more capacitors are a first set of one or more capacitors placed between the first RF terminal and the first switch and a corresponding set of one or more capacitors placed between the n-th switch and the second RF terminal.

7. The unit cell of claim 1, wherein the one or more capacitors comprise a first set of one or more capacitors placed between the i-th and the (i+1)-th switch and a second set of one or more capacitors placed between the (n−

i)-th and the (n−

i+1)-th switch, i=1, 2, . . . .

8. The unit cell of claim 2, wherein the one or more capacitors comprise a first set of one or more capacitors placed between the i-th and the (i+1)-th switch and a second set of one or more capacitors placed between the (n−

i)-th and the (n−

i+1)-th switch, i=1, 2, . . . .

9. The unit cell of claim 1, wherein the second RF terminal is ground.

10. The unit cell of claim 2, wherein the second RF terminal is ground.

11. The unit cell of claim 1, wherein the sub-circuit is a significant bit sub-circuit.

12. An electrical circuit comprising one or more unit cells according to claim 1.

13. A voltage handling method comprising:

providing a plurality of stacked switches, the stacked switches proceeding from a first switch closest to a first terminal and farthest from a second terminal to an n-th switch farthest from the first terminal and closest to the second terminal, the first terminal being a terminal through which a voltage source is coupled to the unit cell; and

coupling the stacked switches in series with one or more capacitors, the one or more capacitors being placed symmetrically with respect to the plurality of stacked switches.

14. The method of claim 13, wherein the first and the second terminal are RF terminals.