SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER

• US 20110043394A1
• Filed: 08/18/2010
• Published: 02/24/2011
• Est. Priority Date: 08/18/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Losi, Marco, Giacomini, Mauro, Farabegoli, Gianluca
• Granted Patent: US 8,264,389 B2
• Time in Patent Office: Days
• US Class Current: 341/120
• CPC Class Codes: H03M 1/1076 Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit
• CPC Class Codes: H03M 1/109 for dc performance, i.e. static testing H03M1/1085 takes precedence
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

A circuit including an analog-to-digital converter having a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components.

Claims

1. An analog-to-digital converter, comprising:

a first generator that generates a first analog value according to a configuration signal when the analog-to-digital converter is operating in a first phase of a test mode;

a digital-to-analog converter adapted to generate a second analog value according to a control signal when the analog-to-digital converter is operating in a second phase of the test mode;

a second generator that generates a digital value from the comparison of the first analog value with respect to the second analog value according to a successive-approximation algorithm when the analog-to-digital converter is operating in the second phase of the test mode;

a controller adapted to receive a signal indicating the test mode, and adapted to;

generate in the first phase the configuration signal;

receive in the second phase the digital value and generate therefrom the control signal for controlling the generation of the second analog value according to the successive-approximation algorithm;

generate, from the digital value, an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter.

2. The analog-to-digital converter according to claim 1 wherein the digital-to-analog converter is a capacitive digital-to-analog converter that includes:

a second plurality of capacitors having a respective terminal connected to a second common terminal;

a second plurality of switches connecting a respective other terminal of the second plurality of capacitors to a low reference voltage or to an high reference voltage; and

wherein the controller is further adapted to generate the control signal for the configuration of the second plurality of switches in order to generate the second analog value on the second common terminal.

3. The analog-to-digital converter according to claim 1 wherein the first generator is a capacitive digital-to-analog converter that comprises:

a first plurality of capacitors having a respective terminal connected to a first common terminal;

a first plurality of switches connecting a respective other terminal of the first plurality of capacitors to a low reference voltage or to an high reference voltage;

wherein the controller is adapted to generate the configuration signal for the configuration of at least part of the first plurality of switches in order to generate the first analog value on the first common terminal.

4. The analog-to-digital converter according to claim 3 wherein the controller is adapted to generate the configuration signal including a sequence of values for the configuration, when the analog-to-digital converter is operating in the first phase, of two switches out of the first plurality of switches, in order to generate a voltage of the first analog value on the first common terminal.

5. The analog-to-digital converter according to claim 4 wherein the sequence of values performs the inversion of the voltage of the other terminal of a capacitor connected to one of the two switches from a first reference voltage to a second reference voltage and to perform at substantially the same time the inversion of the voltage of the other terminal of another capacitor connected to the other one of the two switches from the second reference voltage to the first reference voltage, or vice versa.

6. The analog-to-digital converter according to claim 3 wherein the first generator includes a resistive digital-to-analog converter adapted to generate in the first phase a third analog value selected out of a plurality of analog values according to the configuration signal, wherein the first generator is further adapted to receive in the first phase the third analog value and to sample the third analog value over the first plurality of capacitors, wherein the controller is further adapted to receive in the second phase the digital value and to generate therefrom the control signal for controlling the generation of the second analog value according to a successive-approximation algorithm over the second plurality of capacitors.

7. The analog-to-digital converter according to claim 3 wherein the first generator includes a resistive digital-to-analog converter adapted to generate in the first phase a third analog value selected out of a plurality of analog values according to the configuration signal, wherein the first generator is further adapted to receive in the first phase the third analog value and to sample the third analog value over the first plurality of capacitors, wherein the controller is further adapted to generate the control signal for connecting the second plurality of capacitors to a fixed configuration, such that the digital-to-analog converter is adapted to generate a second fixed analog value, and wherein the controller is further adapted to receive in the second phase the digital value and to generate therefrom the configuration signal for controlling the generation of the first analog value according to a successive-approximation algorithm over the first plurality of capacitors.

8. The analog-to-digital converter according to claim 1 wherein the second generator includes:

a comparator adapted to receive the first analog value and the second analog value, to perform the comparison between the first analog value and the second analog value, and to generate therefrom the value of the bits of the digital value; and

a register adapted to store the digital value.

9. A method for testing the operation of an analog-to-digital converter, the method comprising a first phase and a second phase, the first phase including the steps of:

a) receiving a signal indicating a test mode operation;

b) generating a configuration signal;

c) generating a first analog value according to the configuration signal;

the second phase including the steps of;

d) generating a control signal;

e) generating a second analog value according to the control signal;

f) comparing the first analog value with respect to the second analog value and generating therefrom a digital value according to a successive-approximation algorithm;

g) receiving the digital value and generating therefrom the control signal for controlling the generation of the second analog value according to the successive-approximation algorithm;

h) generating, from the digital value, an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter.

10. The method according to claim 9 wherein step h) includes the steps of:

comparing the digital value with respect to a range of values; and

generating therefrom the alarm signal indicating the failure or the degradation of the performance, in case the digital value is out of the range.

11. An integrated circuit comprising an analog-to-digital converter that includes:

a first generator that generates a first analog value according to a configuration signal when the analog-to-digital converter is operating in a first phase of a test mode;

a digital-to-analog converter adapted to generate a second analog value according to a control signal when the analog-to-digital converter is operating in a second phase of the test mode;

a second generator that generates a digital value from the comparison of the first analog value with respect to the second analog value according to a successive-approximation algorithm when the analog-to-digital converter is operating in the second phase of the test mode; and

a controller adapted to receive a signal indicating the test mode, and adapted to;

generate in the first phase the configuration signal;

receive in the second phase the digital value and generate therefrom the control signal for controlling the generation of the second analog value according to the successive-approximation algorithm; and

generate, from the digital value, an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter.

12. The circuit of claim 11 wherein the digital-to-analog converter is a capacitive digital-to-analog converter that includes:

a second plurality of capacitors having a respective terminal connected to a second common terminal;

a second plurality of switches connecting a respective other terminal of the second plurality of capacitors to a low reference voltage or to an high reference voltage; and

wherein the controller is further adapted to generate the control signal for the configuration of the second plurality of switches in order to generate the second analog value on the second common terminal.

13. The circuit of claim 11 wherein the first generator is a capacitive digital-to-analog converter that comprises:

a first plurality of capacitors having a respective terminal connected to a first common terminal;

a first plurality of switches connecting a respective other terminal of the first plurality of capacitors to a low reference voltage or to an high reference voltage; and

wherein the controller is adapted to generate the configuration signal for the configuration of at least part of the first plurality of switches in order to generate the first analog value on the first common terminal.

14. The circuit of claim 13 wherein the controller is adapted to generate the configuration signal including a sequence of values for the configuration, when the analog-to-digital converter is operating in the first phase, of two switches out of the first plurality of switches, in order to generate a voltage of the first analog value on the first common terminal.

15. The circuit of claim 14 wherein the sequence of values performs the inversion of the voltage of the other terminal of a capacitor connected to one of the two switches from a first reference voltage to a second reference voltage and to perform at substantially the same time the inversion of the voltage of the other terminal of another capacitor connected to the other one of the two switches from the second reference voltage to the first reference voltage, or vice versa.

16. An electronic system comprising:

an analog-to-digital converter comprising;

a first generator that generates a first analog value according to a configuration signal when the analog-to-digital converter is operating in a first phase of a test mode;

a digital-to-analog converter adapted to generate a second analog value according to a control signal when the analog-to-digital converter is operating in a second phase of the test mode;

a second generator that generates a digital value from the comparison of the first analog value with respect to the second analog value according to a successive-approximation algorithm when the analog-to-digital converter is operating in the second phase of the test mode; and

a controller adapted to receive a signal indicating the test mode, and adapted to;

generate in the first phase the configuration signal;

receive in the second phase the digital value and generate therefrom the control signal for controlling the generation of the second analog value according to the successive-approximation algorithm; and

generate, from the digital value, an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter; and

a micro-processor adapted to compare the digital value with respect to a range of values and to generate therefrom the alarm signal indicating the failure or the degradation, in case the digital value is out of the range.

17. The system of claim 16 wherein the digital-to-analog converter is a capacitive digital-to-analog converter that includes:

a second plurality of capacitors having a respective terminal connected to a second common terminal;

a second plurality of switches connecting a respective other terminal of the second plurality of capacitors to a low reference voltage or to an high reference voltage; and

wherein the controller is further adapted to generate the control signal for the configuration of the second plurality of switches in order to generate the second analog value on the second common terminal;

wherein the first generator is a capacitive digital-to-analog converter that comprises;

a first plurality of capacitors having a respective terminal connected to a first common terminal;

a first plurality of switches connecting a respective other terminal of the first plurality of capacitors to a low reference voltage or to an high reference voltage; and

wherein the controller is adapted to generate the configuration signal for the configuration of at least part of the first plurality of switches in order to generate the first analog value on the first common terminal.

18. The system of claim 17 wherein the controller is adapted to generate the configuration signal, including a sequence of values for the configuration, when the analog-to-digital converter is operating in the first phase, of two switches out of the first plurality of switches, in order to generate a voltage of the first analog value on the first common terminal.

19. The system of claim 18 wherein the sequence of values performs the inversion of the voltage of the other terminal of a capacitor connected to one of the two switches from a first reference voltage to a second reference voltage and to perform at substantially the same time the inversion of the voltage of the other terminal of another capacitor connected to the other one of the two switches from the second reference voltage to the first reference voltage, or vice versa.

20. The system of claim 17 wherein the first generator includes a resistive digital-to-analog converter adapted to generate in the first phase a third analog value selected out of a plurality of analog values according to the configuration signal, wherein the first generator is further adapted to receive in the first phase the third analog value and to sample the third analog value over the first plurality of capacitors, wherein the controller is further adapted to receive in the second phase the digital value and to generate therefrom the control signal for controlling the generation of the second analog value according to a successive-approximation algorithm over the second plurality of capacitors.