SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING
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Abstract
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.
276 Citations
34 Claims
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1-14. -14. (canceled)
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15. A method of operating a memory cell having a fin structure including a floating substrate region for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:
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reading and storing data to the floating substrate region of the tin structure while power is applied to the memory cell; transferring the data stored in the floating substrate region to the floating gate or trapping layer when power to the cell is interrupted; and storing the data in the floating gate or trapping layer as non-volatile memory. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of operating an integrated circuit comprising a plurality of memory cells connected in series each having a floating body for storing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory, the method comprising:
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reading and storing data to the floating bodies as volatile memory while power is applied to the device; transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating bodies, when power to the device is interrupted; and storing the data in the floating gates or trapping layers as non-volatile memory. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification