NONVOLATILE MEMORY DEVICE, METHOD FOR PROGRAMMING SAME, AND MEMORY SYSTEM INCORPORATING SAME

• US 20110044113A1
• Filed: 07/01/2010
• Published: 02/24/2011
• Est. Priority Date: 08/18/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JEONG, Jae Yong, KIM, In-Mo
• Application Number:
  US12/828,480
• Publication Number:
  US 20110044113A1
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A nonvolatile memory device performs a program operation on selected memory cells by determining a level of a program voltage based on a degree of deterioration of the memory cells, and executing the program operation using the program voltage.

Claims

1. A method of performing a program operation on memory cells in a nonvolatile memory device, comprising:

determining a level of a program voltage based on a degree of deterioration of the memory cells; and

executing the program operation using the program voltage.

2. The method of claim 1, wherein the degree of deterioration is determined based on a number of program or erase cycles performed on the memory cells.

3. The method of claim 1, wherein the degree of deterioration is detected based on a number of program and erase cycles performed on the memory cells.

4. The method of claim 1, wherein determining the level of the program voltage comprises adjusting an increment of the program voltage to be applied between successive program loops of the program operation.

5. The method of claim 4, further comprising:

determining a level of a verify voltage for the program operation based on the increment of the program voltage.

6. The method of claim 4, further comprising:

determining a number of program or erase cycles performed on the memory cells;

setting the increment of the program voltage to a first value upon determining that the number of program or erase cycles is greater than a predetermined value, and

setting the increment of the program voltage to a second value greater than the first value upon determining that the number of program or erase cycles is less than or equal to the predetermined value.

7. The method of claim 6, further comprising:

setting a verify voltage for the program operation to a first level where the increment of the program voltage is set to the first value, and setting the verify voltage to a second level lower than the first level where the increment of the program voltage is set to the second value.

8. The method of claim 1, wherein the program operation is executed with a high voltage received from an external source depending on the degree of deterioration of the memory cells.

9. The method of claim 1, wherein the nonvolatile memory device is a multi-level cell flash memory device.

10. The method of claim 1, wherein the program operation is executed using incremental step pulse programming.

11. A nonvolatile memory device comprising:

a memory cell array;

a read/write circuit configured to perform program and read operations on the memory cell array;

a voltage generator configured to provide voltages to the memory cell array; and

control logic configured to control the read/write circuit and the voltage generator,

wherein the control logic controls the voltage generator to adjust a program voltage depending on a degree of deterioration of memory cells in the memory cell array.

12. The nonvolatile memory device of claim 11, wherein the degree of deterioration of the memory cells is detected based on a number of program and erase cycles that have been performed on the memory cells.

13. The nonvolatile memory device of claim 12, wherein the control logic stores the number of program and erase cycles that have been performed on the memory cells.

14. The nonvolatile memory device of claim 11, wherein the control logic is configured to program the memory cells using an acceleration mode wherein a high voltage supplied from an external source is provided to the memory cell based on the degree of deterioration of the memory cells.

15. The nonvolatile memory device of claim 11, wherein the control logic controls the read/write circuit to perform a program operation using incremental step pulse programming with the adjusted program voltage.

16. The nonvolatile memory device of claim 15, wherein the adjusted program voltage is incremented with a first or second increment in successive program loops of the program operation depending on a number of program or erase cycles that have been performed previously on the memory cells.

17. The nonvolatile memory device of claim 11, wherein the memory cell array comprises flash memory cells arranged in a NAND flash configuration.

18. A memory system comprising:

a nonvolatile memory device; and

a controller configured to control the nonvolatile memory device,

wherein the nonvolatile memory device comprises;

a memory cell array;

a read/write circuit configured to perform read and write operations on the memory cell array;

a voltage generator configured to provide voltages to the memory cell array; and

control logic configured to control the read and write circuit and the voltage generator,

wherein the control logic controls the voltage generator such that a program voltage is adjusted depending on a degree of deterioration of memory cells of the memory cell array.

19. The memory system of claim 18, wherein:

the nonvolatile memory device and the controller are incorporated in a solid-state drive (SSD).

20. The memory system of claim 18, wherein the control logic controls the voltage generator to adjust a program verify voltage based on a number of program or erase operations that have been performed previously on selected memory cells to be programmed in a program operation.