SHIFT REGISTER

• US 20110044423A1
• Filed: 11/09/2009
• Published: 02/24/2011
• Est. Priority Date: 08/21/2009
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Chen, Yung-Chih, Lin, Chih-Lung, Tu, Chun-Da
• Granted Patent: US 8,081,731 B2
• Time in Patent Office: Days
• US Class Current: 377/64
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register includes a plurality of electrically connected shift units. Each shift unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit outputs a first signal to an output node according to the first signal and a voltage of a driving node. The pull-up driving drives the pull-up circuit according to an output voltage of the previous shift unit. The pull-down driving circuit outputs a low level voltage to the driving node and the output node according to the first signal and a second signal. The pull-down circuit resets the pull-up driving circuit according to the voltage of the output node and outputs the low level voltage to the output node and the driving node according to a third signal and a fourth signal.

Claims

1. A shift register, comprising a plurality of electrically connected shift units, wherein each shift unit comprises:

a pull-up circuit, for outputting a first signal to an output node according to the first signal and a voltage level of a driving node;

a pull-up driving circuit, electrically connected to the pull-up circuit, for driving the pull-up circuit according to an output voltage of the previous shift unit;

a pull-down driving circuit, electrically connected to the pull-up driving circuit, for outputting a low voltage level to the driving node and the output node, according to the first signal and a second signal; and

a pull-down circuit, electrically connected to the pull-up circuit and the pull-up driving circuit, for resetting the pull-up driving circuit according to the voltage level of the output node, and outputting the low voltage level to the driving node and the output node according to a third signal and a fourth signal.

2. The shift register of claim 1, wherein the pull-up circuit comprises:

a first transistor, comprising a first end for receiving the first signal, a control end electrically connected to the driving node, and a second end electrically connected to the output node.

3. The shift register of claim 2, wherein the pull-up driving circuit comprises:

a second transistor, comprising a first end electrically connected to the output node of the previous shift unit for receiving the output voltage, a control end electrically connected to the first end, and a second end electrically connected to the driving node.

4. The shift register of claim 3, wherein the pull-down driving circuit comprises:

a third transistor, comprising a first end for receiving the first signal, a control end electrically connected to the first end, and a second end electrically connected to a first node;

a fourth transistor, comprising a first end electrically connected to the first node, a control end electrically connected to the output node and a second end for receiving the low voltage level;

a fifth transistor, comprising a first end electrically connected to the output node, a control end electrically connected to the first node, and a second end for receiving the low voltage level;

a sixth transistor, comprising a first end electrically connected to the driving node, a control end for receiving the first signal, and a second end electrically connected to the output node; and

a seventh transistor, comprising a first end electrically connected to the output node, a control end for receiving the second signal, and a second end for receiving the low voltage level.

5. The shift register of claim 4, wherein the pull-down circuit comprises:

an eighth transistor, comprising a first end electrically connected to the output node, a control end for receiving the third signal, and a second end for receiving the low voltage level;

a ninth transistor, comprising a first end electrically connected to the driving node, a control end for receiving the third signal, and a second end for receiving the low voltage level;

a tenth transistor, comprising a first end electrically connected to the first end of the second transistor, a control end electrically connected to the output node, and a second end for receiving the low voltage level; and

a eleventh transistor, comprising a first end electrically connected to the output node, a control end for receiving the fourth signal, and a second end for receiving the low voltage level.

6. The shift register of claim 5, wherein the first signal, the second signal, the third signal and the fourth signal are sequential pulse signals.

7. The shift register of claim 5, wherein the pull-down circuit further comprises:

a twelfth transistor, comprising a first end electrically connected to the output node, a control end for receiving a fifth signal, and a second end for receiving the low voltage level.

8. The shift register of claim 7, wherein the first signal, the second signal, the third signal, the fourth signal and the fifth signal are sequential pulse signals.

9. The shift register of claim 1, wherein the pull-up circuit comprises:

a first transistor, comprising a first end for receiving the first signal, a control end electrically connected to the driving node, and a second end electrically connected to the output node; and

a thirteenth transistor, comprising a first end for receiving the first signal, a control end electrically connected to the driving node, and a second end electrically connected to a transmitting node.

10. The shift register of claim 9, wherein the pull-up driving circuit comprises:

a second transistor, comprising a first end electrically connected to the transmitting node of the previous shift unit for receiving the output voltage, a control end electrically connected to the first end, and a second end electrically connected to the driving node.

11. The shift register of claim 10, wherein the pull-down driving circuit comprises:

a third transistor, comprising a first end for receiving the first signal, a control end electrically connected to the first end, and a second end electrically connected to a first node;

a fourth transistor, comprising a first end electrically connected to the first node, a control end electrically connected to the output node, and a second end for receiving the low voltage level;

a fifth transistor, comprising a first end electrically connected to the output node, a control end electrically connected to the first node, and a second end for receiving the low voltage level;

a sixth transistor, comprising a first end electrically connected to the driving node, a control end for receiving the first signal, and a second end electrically connected to the output node; and

a seventh transistor, comprising a first end electrically connected to the output node, a control end for receiving the second signal, and a second end for receiving the low voltage level.

12. The shift register of claim 11, wherein the pull-down circuit comprises:

an eighth transistor, comprising a first end electrically connected to the output node, a control end for receiving the third signal, and a second end for receiving the low voltage level;

a ninth transistor, comprising a first end electrically connected to the driving node, a control end for receiving the third signal, and a second end for receiving the low voltage level;

a tenth transistor, comprising a first end electrically connected to the first end of the second transistor, a control end electrically connected to the output node, and a second end for receiving the low voltage level;

a eleventh transistor, comprising a first end electrically connected to the output node, a control end for receiving the fourth signal, and a second end for receiving the low voltage level;

a fourteenth transistor, comprising a first end electrically connected to the transmitting node, a control end for receiving the fourth signal, and a second end for receiving the low voltage level.

13. The shift register of claim 12, wherein the first signal, the second signal, the third signal and the fourth signal are sequential pulse signals.

14. The shift register of claim 12, wherein the pull-down circuit further comprises:

a twelfth transistor, comprising a first end electrically connected to the output node, a control end for receiving a fifth signal, and a second end for receiving the low voltage level.

15. The shift register of claim 14, wherein the first signal, the second signal, the third signal, the fourth signal and the fifth signal are sequential pulse signals.

16. The shift register of claim 1, wherein the pull-down driving circuit comprises:

a sixth transistor, comprising a first end electrically connected to the driving node, a control end for receiving the first signal, and a second end electrically connected to the output node; and

a seventh transistor, comprising a first end electrically connected to the output node, a control end for receiving the second signal, and a second end for receiving the low voltage level.

17. The shift register of claim 1, wherein the pull-down circuit comprises:

a ninth transistor, comprising a first end electrically connected to the driving node, a control end for receiving the third signal, and a second end for receiving the low voltage level; and

a tenth transistor, comprising a first end electrically connected to the first end of the second transistor, a control end electrically connected to the output node, and a second end for receiving the low voltage level.