Method of forming active region structure

• US 20110045643A1
• Filed: 05/20/2010
• Published: 02/24/2011
• Est. Priority Date: 08/18/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Jun-Ho, Kim, Byeong-Soo, Kim, Hyung-Yong, Shin, Kyoung-Sub, Cho, Hong
• Granted Patent: US 8,420,453 B2
• Time in Patent Office: Days
• US Class Current: 438/129
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region

Abstract

A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

Claims

1. A method of forming an active region structure, comprising:

preparing a semiconductor substrate including a cell array region and a peripheral circuit region;

forming preliminary cell active regions in the cell array region of the semiconductor substrate; and

forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

2. The method as claimed in claim 1, wherein forming the preliminary cell active regions includes:

forming a pad layer to cover an entire surface of the semiconductor substrate;

forming first buffer patterns and a buffer layer on the pad layer in the cell array region and the peripheral circuit region of the semiconductor substrate, respectively;

forming sacrificial patterns between the first buffer patterns;

forming second buffer patterns in the sacrificial patterns, respectively, the first and second buffer patterns having a line shape and corresponding to the preliminary cell active regions; and

forming first cell trenches in the cell array region of the semiconductor substrate to correspond to the sacrificial patterns.

3. The method as claimed in claim 2, wherein forming the first cell trenches includes:

etching the sacrificial patterns and the pad layer disposed under the sacrificial patterns using the first and second buffer patterns and the buffer layer as an etch mask to expose the semiconductor substrate, such that the pad layer is divided into cell pad patterns in the cell array region; and

etching the first and second buffer patterns, the buffer layer, and the semiconductor substrate using the cell pad patterns of the cell array region and the pad layer of the peripheral circuit region as an etch mask, such that the first and second buffer patterns and the buffer layer are removed from the cell pad patterns and the pad layer.

4. The method as claimed in claim 3, wherein forming the cell active regions and the at least one peripheral active region includes:

forming a cell definition pattern and a peripheral definition pattern on the cell pad patterns of the cell array region and the pad layer of the peripheral circuit region, respectively, to fill the first cell trenches, the cell definition pattern having isolation holes on the cell pad patterns, and the peripheral definition pattern defining the at least one peripheral active region;

etching the cell pad patterns disposed within the isolation holes and the pad layer disposed adjacent to the peripheral definition pattern using the cell definition pattern and the peripheral definition pattern as an etch mask, such that the pad layer of the peripheral circuit region is patterned to form at least one peripheral pad pattern;

etching the preliminary active regions disposed within the isolation holes and the semiconductor substrate disposed adjacent to the peripheral definition pattern using the cell definition pattern, the peripheral definition pattern, and the at least one peripheral pad pattern as an etch mask to form second cell trenches in the cell array region and peripheral trenches in the peripheral circuit region; and

removing the cell definition pattern and the peripheral definition pattern from the semiconductor substrate.

5. The method as claimed in claim 4, wherein the first and second cell trenches define the cell active regions under the cell pad patterns of the cell array region and extend to substantially the same depth from a top surface to a bottom surface of the semiconductor substrate, and the peripheral trenches define the at least one peripheral active region under the at least one peripheral pad pattern of the peripheral circuit region and are formed to substantially the same depth as the first and second cell trenches.

6. The method as claimed in claim 5, wherein each of the second cell trenches is formed between selected cell active regions disposed opposite each other on both sides of one selected isolation hole in a widthwise direction of the first and second buffer patterns, and a width of each of the first cell trenches is smaller than a width of each of the second cell trenches in the widthwise direction of the first and second buffer patterns.

7. The method as claimed in claim 6, wherein two adjacent first cell trenches overlap one selected second cell trench, the width of each of the first cell trenches is substantially the same as or different from a width of each of the isolation holes in the widthwise direction of the first and second buffer patterns, and each of the isolation holes is defined by an opening area of the one selected second cell trench.

8. The method as claimed in claim 7, wherein the cell and peripheral definition patterns are formed of carbon (C), a C-containing single material, or a C-containing stacked material.

9. The method as claimed in claim 1, wherein forming the preliminary cell active regions includes:

forming a pad layer to cover an entire surface of the semiconductor substrate;

forming first cell pad patterns on the cell array region of the semiconductor substrate, the first cell pad patterns having a line shape;

dividing the first cell pad patterns into second cell pad patterns, the second cell pad patterns having a line shape and corresponding to the preliminary cell active regions; and

etching the semiconductor substrate of the cell array region using the second cell pad patterns and the pad layer of the peripheral circuit region as an etch mask to form first cell trenches in the semiconductor substrate, such that the second cell pad patterns and the pad layer of the peripheral circuit region are partially etched.

10. The method as claimed in claim 9, wherein forming the cell active regions and the at least one peripheral active region includes:

forming a cell definition pattern on the second cell pad patterns in the cell array region to fill the first cell trenches, such that the cell definition pattern has isolation holes formed on the second cell pad patterns;

forming a peripheral definition pattern on the pad layer in the peripheral circuit region, such that the peripheral definition pattern defines the at least one peripheral active region;

etching the second cell pad patterns disposed in the isolation holes and the pad layer disposed adjacent to the peripheral definition pattern using the cell definition pattern and the peripheral definition pattern as an etch mask, such that the pad layer of the peripheral circuit region is patterned to form at least one peripheral pad pattern;

etching the preliminary active regions disposed in the isolation holes and the semiconductor substrate disposed adjacent to the peripheral definition pattern using the cell definition pattern, the peripheral definition pattern, and the at least one peripheral pad pattern as an etch mask to form second cell trenches in the cell array region and peripheral trenches in the peripheral circuit region; and

removing the cell definition pattern and the peripheral definition pattern from the semiconductor substrate.

11-18. -18. (canceled)